M52S128324A-7BG ELITE SEMICONDUCTOR, M52S128324A-7BG Datasheet - Page 10

• Manufacturer Part Number: M52S128324A-7BG
• Description: IC, SDRAM, 128MBIT, 143MHZ, FBGA-90
• Manufacturer: ELITE SEMICONDUCTOR

Specifications of M52S128324A-7BG

• Memory Type: DRAM - Sychronous
• Memory Configuration: 2M X 16
• Ic Interface Type: Parallel
• Memory Case Style: FBGA
• No. Of Pins: 90
• Operating Temperature Range: 0°C To +70°C
• Frequency: 133MHz
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Page Size: 128MB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ESMT
Note :
Elite Semiconductor Memory Technology Inc.
Register
Refresh
Column Address
Column Address
Precharge
Clock Suspend or
Active Power Down
Precharge Power Down Mode
DQM
No Operating Command
Read &
Write &
1.OP Code : Operating Code
2.MRS can be issued only at all banks precharge state.
3.Auto refresh functions are as same as CBR refresh of DRAM.
4.BA0~BA1 : Bank select addresses.
Bank Active & Row Addr.
A0~A11 & BA0~BA1 : Program keys. (@ MRS)
A new command can be issued after 2 CLK cycles of MRS.
The automatical precharge without row precharge of command is meant by “Auto”.
Auto/self refresh can be issued only at all banks idle state.
If both BA1 and BA0 are “Low” at read ,write , row active and precharge ,bank A is selected.
If both BA1 is “Low” and BA0 is “High” at read ,write , row active and precharge ,bank B is selected.
COMMAND
Burst Stop
Mode Register set
Auto Refresh
Self
Refresh
Bank Selection
All Banks
Auto Precharge Disable
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Enable
Entry
Exit
Entry
Entry
Exit
Exit
CKEn-1 CKEn
H
H
H
H
H
H
H
H
H
H
H
L
L
L
(V = Valid , X = Don’t Care. H = Logic High , L = Logic Low )
X
H
H
X
X
X
X
X
H
H
X
L
L
L
CS RAS CAS
H
H
X
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
V
H
V
X
H
L
L
X
L
L
X
X
X
X
X
H
X
H
H
H
X
V
X
X
H
X
V
X
H
L
L
L
L
WE
H
H
X
H
H
X
V
X
X
H
X
V
X
H
L
L
L
L
DQM BA0,1 A10/AP
Publication Date: Mar. 2008
Revision: 1.3
X
X
X
X
X
X
X
X
X
X
X
X
X
V
X
M52S128324A
V
V
V
V
X
SIMPLIFIED
TABLE
OP CODE
Row Address
H
H
H
L
L
L
X
X
X
X
X
X
X
Address
(A0~A7)
Column
Column
Address
(A0~A7)
A9~A0
10/47
X
TRUTH
Note
1,2
4,5
4,5
3
3
3
3
4
4
6
7