M52S128168A-7.5TG ELITE SEMICONDUCTOR, M52S128168A-7.5TG Datasheet - Page 23

• Manufacturer Part Number: M52S128168A-7.5TG
• Description: IC, SDRAM, 128MBIT, 133MHZ, TSOP-54
• Manufacturer: ELITE SEMICONDUCTOR

Specifications of M52S128168A-7.5TG

• Memory Type: DRAM - Sychronous
• Memory Configuration: 2M X 16
• Ic Interface Type: Parallel
• Memory Case Style: TSOP
• No. Of Pins: 54
• Operating Temperature Range: 0°C To +70°C
• Frequency: 133MHz
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Page Size: 128MB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ESMT
6. Precharge
.
7. Auto Precharge
*Note : 1. t
Elite Semiconductor Memory Technology Inc.
C M D
C L K
D Q
C M D
C L K
D Q
2. Number of valid output data after row precharge : 1,2 for CAS Latency = 2,3 respectively.
3. The row active command of the precharge bank can be issued after t
1 ) N o r m a l W r i t e ( B L = 4 )
The new read/write command of other activated bank can be issued from this point.
At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal.
RDL
1 ) N o r m a l W r i t e ( B L = 4 )
W R
: Last data in to row precharge delay.
D 0
W R
D 0
D 1
D 1
D 2
D 2
D 3
A u t o P r e c h a r g e s t a r t s
D 3
t
* N o t e 1
R D L
t
R D L ( m i n )
P R E
* N o t e 3
D Q ( C L 3 )
D Q ( C L 2 )
D Q ( C L 3 )
D Q ( C L 2 )
C M D
C L K
C M D
C M D
C L K
2 ) N o r m a l R e a d ( B L = 4 )
2 ) N o r m a l R e a d ( B L = 4 )
R D
R D
RP
from this point.
Publication Date: Oct. 2007
Q 0
D 0
Revision: 1.1
A u t o P r e c h a r g e s t a r t s
Q 0
Q 1
D 1
D 0
M52S128168A
P R E
P R E C L = 3
Q2
Q 1
D 2
D 1
* N o t e 3
C L = 2
Q 3
Q2
D 3
D 2
* N o t e 2
* N o t e 2
Q3
D 3
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