IS61LV12816L-10TL INTEGRATED SILICON SOLUTION (ISSI), IS61LV12816L-10TL Datasheet - Page 11

• Manufacturer Part Number: IS61LV12816L-10TL
• Description: IC, SRAM, 2MBIT, 10NS, TSOP-2-44
• Manufacturer: INTEGRATED SILICON SOLUTION (ISSI)

Specifications of IS61LV12816L-10TL

• Memory Size: 2Mbit
• Memory Configuration: 128K X 16
• Access Time: 10ns
• Supply Voltage Range: 3V To 3.6V
• Memory Case Style: TSOP-2
• No. Of Pins: 44
• Operating Temperature Range: 0°C To +70°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IS61LV12816L
Integrated Silicon Solution, Inc. — www.issi.com —
Rev. F
10/27/05
WRITE CYCLE NO. 4
Notes:
1. The internal Write time is defined by the overlap of CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be
2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state.
3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function.
in valid states to initiate a Write, but any can be deasserted to terminate the Write. The t
referenced to the rising or falling edge of the signal that terminates the Write.
ADDRESS
UB, LB
D
OUT
WE
D
OE
CE
IN
LOW
DATA UNDEFINED
(LB, UB Controlled, Back-to-Back Write)
t
HZWE
ADDRESS 1
t
SD
t
t
WORD 1
SA
WC
t
PBW
HIGH-Z
DATA
VALID
IN
1-800-379-4774
t
t
HD
HA
t
SA
ADDRESS 2
t
t
(1,3)
SD
WC
WORD 2
t
PBW
DATA
VALID
IN
t
LZWE
SA
t
HD
t
, t
HA
HA
, t
SD
, and t
UB_CEWR4.eps
HD
ISSI
timing is
11
®