AT80C51RD2-SLSUM Atmel, AT80C51RD2-SLSUM Datasheet - Page 13

• Manufacturer Part Number: AT80C51RD2-SLSUM
• Description: MCU, 8BIT, 8051, 5V, SPI, 20MHZ, 44PLCC
• Manufacturer: Atmel

Specifications of AT80C51RD2-SLSUM

• Controller Family/series: (8051) 8052
• No. Of I/o's: 32
• Ram Memory Size: 1280Byte
• Cpu Speed: 40MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 5
• Core Size: 8bit
• Oscillator Type: External Only
• Processor Series: AT80x
• Core: 8051
• Data Bus Width: 8 bit
• Program Memory Type: ROMLess
• Data Ram Size: 1280 B
• Interface Type: UART, SPI
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: PLCC
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• Cpu Family: AT80
• Device Core: 8051
• Device Core Size: 8b
• Frequency (max): 40MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 1.25KB
• # I/os (max): 32
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 5-2.
4188F–8051–01/08
XTAL1
XTAL1:2
X2 bit
CPU clock
Mode Switching Waveforms
STD Mode
Figure 5-1.
The X2 bit in the CKCON register
tion to 6 clock cycles and vice versa. At reset, the standard speed is activated (STD mode).
Setting this bit activates the X2 feature (X2 mode).
Note:
Table 5-2.
Bit Number
7
-
7
6
5
In order to prevent any incorrect operation while operating in X2 mode, user must be aware that all
peripherals using clock frequency as time reference (UART, timers, PCA...) will have their time ref-
erence divided by two. For example a free running timer generating an interrupt every 20 ms will
then generate an interrupt every 10 ms. UART with 4800 baud rate will have 9600 baud rate.
XTAL1
Mnemonic
Clock Generation Diagram
CKCON Register
CKCON - Clock Control Register (8Fh)
6
Bit
-
F
-
-
-
XTAL
Description
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5
-
2
X2 Mode
(Table
XTAL1:2
4
-
5-2) allows to switch from 12 clock cycles per instruc-
CKCON reg
X2
0
1
3
-
F
OSC
AT/TS8xC51Rx2
2
-
CPU control
state machine: 6 clock cycles.
STD Mode
1
-
X2
0
13