AT80C51RD2-SLSUM Atmel, AT80C51RD2-SLSUM Datasheet - Page 18

• Manufacturer Part Number: AT80C51RD2-SLSUM
• Description: MCU, 8BIT, 8051, 5V, SPI, 20MHZ, 44PLCC
• Manufacturer: Atmel

Specifications of AT80C51RD2-SLSUM

• Controller Family/series: (8051) 8052
• No. Of I/o's: 32
• Ram Memory Size: 1280Byte
• Cpu Speed: 40MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 5
• Core Size: 8bit
• Oscillator Type: External Only
• Processor Series: AT80x
• Core: 8051
• Data Bus Width: 8 bit
• Program Memory Type: ROMLess
• Data Ram Size: 1280 B
• Interface Type: UART, SPI
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: PLCC
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• Cpu Family: AT80
• Device Core: 8051
• Device Core Size: 8b
• Frequency (max): 40MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 1.25KB
• # I/os (max): 32
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 6-1.
18
FF(RA, RB, RC)/2FF (RD)
AT/TS8xC51Rx2
Internal and External Data Memory Address
00
The stack pointer (SP) may be located anywhere in the 256 bytes RAM (lower and upper RAM)
internal data memory. The stack may not be located in the XRAM.
Table 6-1.
1.
address bits (DPL) with data. MOVX @ Ri and MOVX @DPTR will generate either read or
write signals on P3.6 (WR) and P3.7 (RD).
256 bytes
EXTRAM
Symbol
XRAM
AO
-
User software should not write 1s to reserved bits. These bits may be used in future 8051 family
products to invoke new features. In that case, the reset or inactive value of the new bit will be 0,
and its active value will be 1. The value read from a reserved bit is indeterminate.
Address 08EH
AUXR
Auxiliary Register
Function
Not implemented, reserved for future use.
Disable/Enable ALE
Internal/External RAM (00H-FFH) access using MOVX @ Ri/ @ DPTR
EXTRAM
FF
80
00
Reset value
AO
0
1
0
1
indirect accesses
direct or indirect
128 bytes
128 bytes
accesses
Internal
Internal
Upper
Lower
Ram
Ram
Operating Mode
ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if X2 mode
is used)
ALE is active only during a MOVX or MOVC instruction
Operating Mode
Internal XRAM access using MOVX @ Ri/ @ DPTR
External data memory access
AUXR
X
-
FF
80
0100 (RA, RB, RC) or 0300 (RD)
X
-
direct accesses
Function
Register
Special
(1)
X
-
X
-
FFFF
X
0000
-
X
-
External
Memory
Data
EXTRAM
0
4188F–8051–01/08
AO
0