UPD78F1154GK-GAK-AX NEC, UPD78F1154GK-GAK-AX Datasheet - Page 44

• Manufacturer Part Number: UPD78F1154GK-GAK-AX
• Description: 16BIT MCU, 128K FLASH, 8K RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F1154GK-GAK-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 70
• Ram Memory Size: 8192Byte
• Cpu Speed: 20MHz
• No. Of Timers: 9
• No. Of: RoHS Compliant
• Core Size: 16bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

44
7.6 Clock Output/Buzzer Output Controller
supply to peripheral ICs.
The clock output controller is intended for carrier output during remote controlled transmission and clock output for
Buzzer output is a function to output a square wave of buzzer frequency.
One pin can be used to output a clock or buzzer sound.
Two output pins, PCLBUZ0 and PCLBUZ1, are available.
PCLBUZ0 outputs a clock selected by clock output select register 0 (CKS0).
PCLBUZ1 outputs a clock selected by clock output select register 1 (CKS1).
Note
The clock output/buzzer output controller uses the following two types of registers.
(1) Clock output select register 0 (CKS0)
(2) Clock output select register 1 (CKS1)
f
This register is used to enable or disable clock output or output of the pin that outputs a buzzer frequency
(PCLBUZ0), and set an output clock.
This register is used to enable or disable clock output or output of the pin that outputs a buzzer frequency
(PCLBUZ1), and set an output clock.
MAIN
f
SUB
PCLOE1
PCLOE0
The PCLBUZ0 and PCLBUZ1 pins can output a clock of up to 10 MHz at 2.7 V ≤ V
exceeding 5 MHz at V
0
0
Figure 7-5. Block Diagram of Clock Output/Buzzer Output Controller
Prescaler
Prescaler
5
8
0
0
3
8
DD
Internal bus
f
f
Internal bus
MAIN
0
MAIN
0
< 2.7 V is prohibited.
f
f
MAIN
/2
/2
MAIN
f
f
SUB
SUB
11
11
CSEL1 CCS12 CCS11 CCS10
CSEL0 CCS02 CCS01 CCS00
to f
to f
to f
Clock output select register 0 (CKS0)
Preliminary Product Information U17892EJ2V0PM
Clock output select register 1 (CKS1)
to f
to f
to f
MAIN
MAIN
MAIN
MAIN
SUB
SUB
/2
/2
/2
/2
/2
/2
13
7
13
4
7
4
Clock/buzzer
Clock/buzzer
controller
controller
PCLOE1
PCLOE0
Output latch
Output latch
(P141)
(P140)
PM141
PM140
PCLBUZ1
PCLBUZ0
DD
Note
Note
. Setting a clock
/INTP7/P141
/INTP6/P140
78K0R/KF3