UPD78F1154GK-GAK-AX NEC, UPD78F1154GK-GAK-AX Datasheet - Page 49

16BIT MCU, 128K FLASH, 8K RAM, SMD

UPD78F1154GK-GAK-AX

Manufacturer Part Number
UPD78F1154GK-GAK-AX
Description
16BIT MCU, 128K FLASH, 8K RAM, SMD
Manufacturer
NEC
Datasheet

Specifications of UPD78F1154GK-GAK-AX

Controller Family/series
UPD78F
No. Of I/o's
70
Ram Memory Size
8192Byte
Cpu Speed
20MHz
No. Of Timers
9
No. Of
RoHS Compliant
Core Size
16bit
Program Memory Size
128KB
Oscillator Type
External, Internal

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD78F1154GK-GAK-AX
Manufacturer:
NEC
Quantity:
100
(2) UART
(3) Simplified IIC
This is a start-stop synchronization function using two lines: serial data transmission (TxD) and serial data
reception (RxD) lines. It transmits or receives data in asynchronization with the party of communication (by
using an internal baud rate). Full-duplex UART communication can be realized by using two channels, one
dedicated to transmission (even channel) and the other to reception (odd channel).
[Data transmission/reception]
[Interrupt function]
[Error detection flag]
The LIN-bus is accepted in UART3 (2, 3 channels of unit 1)
[LIN-bus functions]
This is a clocked communication function to communicate with two or more devices by using two lines: serial
clock (SCL) and serial data (SDA).
[Data transmission/reception]
[Interrupt function]
[Error detection flag]
* [Functions not supported by simplified IIC]
Remark To use an IIC bus of full function, refer to 7.10 Serial Interface IIC0.
• Data length of 5, 7 or 8 bits
• Select the MSB/LSB first
• Level setting of transmit/receive data
• Parity bit appending and parity check functions
• Stop bit appending
• Transfer end interrupt/buffer empty interrupt
• Error interrupt in case of framing error, parity error, or overrun error
• Framing error, parity error, or overrun error
• Wake-up signal detection
• Sync break field (SBF) detection
• Sync field measurement, baud rate calculation
• Master transmission, master reception (only master function with a single master)
• ACK output and ACK detection functions
• Data length of 8 bits (When an address is transmitted, the address is specified by the higher 7 bits, and
• Manual generation of start condition and stop condition
• Transfer end interrupt
• Parity error (ACK error)
• Slave transmission, slave reception
• Arbitration loss detection function
• Wait detection and wait output functions
the least significant bit is used for R/W control.)
Preliminary Product Information U17892EJ2V0PM
External interrupt (INTP0) or Timer array unit (TAU)
is used.
78K0R/KF3
49

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