ST7FLITE05Y0B6 FARNELL, ST7FLITE05Y0B6 Datasheet - Page 52
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ST7FLITE05Y0B6
Manufacturer Part Number
ST7FLITE05Y0B6
Description
IC, 8BIT MCU, ST7, 16MHZ, DIP-16
Manufacturer
FARNELL
Datasheet
1.ST7FLITE05Y0B6.pdf
(124 pages)
Specifications of ST7FLITE05Y0B6
Controller Family/series
ST7
No. Of I/o's
13
Ram Memory Size
128Byte
Cpu Speed
16MHz
No. Of Timers
2
Interface
SPI
Core Size
8 Bit
Program Memory Size
1.5 Kb
Peripherals
ADC, PWM, Timer
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ST7FLITE05Y0B6
Manufacturer:
ST
Quantity:
20 000
ST7LITE0xY0, ST7LITESxY0
LITE TIMER (Cont’d)
11.1.6 Register Description
LITE TIMER CONTROL/STATUS REGISTER
(LTCSR)
Read / Write
Reset Value: 0x00 0000 (x0h)
Bit 7 = ICIE Interrupt Enable
This bit is set and cleared by software.
0: Input Capture (IC) interrupt disabled
1: Input Capture (IC) interrupt enabled
Bit 6 = ICF Input Capture Flag
This bit is set by hardware and cleared by software
by reading the LTICR register. Writing to this bit
does not change the bit value.
0: No input capture
1: An input capture has occurred
Note: After an MCU reset, software must initialise
the ICF bit by reading the LTICR register
Bit 5 = TB Timebase period selection
This bit is set and cleared by software.
0: Timebase period = t
1: Timebase period = t
Bit 4 = TBIE Timebase Interrupt enable
This bit is set and cleared by software.
0: Timebase (TB) interrupt disabled
1: Timebase (TB) interrupt enabled
Bit 3 = TBF Timebase Interrupt Flag
This bit is set by hardware and cleared by software
reading the LTCSR register. Writing to this bit has
no effect.
Table 13. Lite Timer Register Map and Reset Values
52/124
1
ICIE
Address
MHz)
7
(Hex.)
0B
0C
ICF
LTCSR
Reset Value
LTICR
Reset Value
Register
TB
Label
TBIE
OSC
OSC
TBF
* 8000 (1ms @ 8 MHz)
* 16000 (2ms @ 8
ICR7
ICIE
7
0
0
WDGR WDGE WDGD
ICR6
ICF
6
x
0
0
ICR5
TB
5
0
0
0: No counter overflow
1: A counter overflow has occurred
Bit 2 = WDGRF Force Reset/ Reset Status Flag
This bit is used in two ways: it is set by software to
force a watchdog reset. It is set by hardware when
a watchdog reset occurs and cleared by hardware
or by software. It is cleared by hardware only when
an LVD reset occurs. It can be cleared by software
after a read access to the LTCSR register.
0: No watchdog reset occurred.
1: Force a watchdog reset (write), or, a watchdog
Bit 1 = WDGE Watchdog Enable
This bit is set and cleared by software.
0: Watchdog disabled
1: Watchdog enabled
Bit 0 = WDGD Watchdog Reset Delay
This bit is set by software. It is cleared by hard-
ware at the end of each t
0: Watchdog reset not delayed
1: Watchdog reset delayed
LITE TIMER INPUT CAPTURE REGISTER
(LTICR)
Read only
Reset Value: 0000 0000 (00h)
Bit 7:0 = ICR[7:0] Input Capture Value
These bits are read by software and cleared by
hardware after a reset. If the ICF bit in the LTCSR
is cleared, the value of the 8-bit up-counter will be
captured when a rising or falling edge occurs on
the LTIC pin.
ICR7
reset occurred (read).
7
TBIE
ICR4
4
0
0
ICR6
ICR3
TBF
ICR5
3
0
0
ICR4
WDGRF
ICR2
2
0
0
WDG
ICR3
period.
WDGE
ICR2
ICR1
1
0
0
ICR1
WDGD
ICR0
0
0
0
ICR0
0