ST7FLITE05Y0B6 FARNELL, ST7FLITE05Y0B6 Datasheet - Page 56
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ST7FLITE05Y0B6
Manufacturer Part Number
ST7FLITE05Y0B6
Description
IC, 8BIT MCU, ST7, 16MHZ, DIP-16
Manufacturer
FARNELL
Datasheet
1.ST7FLITE05Y0B6.pdf
(124 pages)
Specifications of ST7FLITE05Y0B6
Controller Family/series
ST7
No. Of I/o's
13
Ram Memory Size
128Byte
Cpu Speed
16MHz
No. Of Timers
2
Interface
SPI
Core Size
8 Bit
Program Memory Size
1.5 Kb
Peripherals
ADC, PWM, Timer
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ST7FLITE05Y0B6
Manufacturer:
ST
Quantity:
20 000
ST7LITE0xY0, ST7LITESxY0
12-BIT AUTORELOAD TIMER (Cont’d)
11.2.6 Register Description
TIMER CONTROL STATUS REGISTER (ATC-
SR)
Read / Write
Reset Value: 0000 0000 (00h)
Bit 7:5 = Reserved, must be kept cleared.
Bit 4:3 = CK[1:0] Counter Clock Selection.
These bits are set and cleared by software and
cleared by hardware after a reset. They select the
clock frequency of the counter.
Bit 2 = OVF Overflow Flag.
This bit is set by hardware and cleared by software
by reading the ATCSR register. It indicates the
transition of the counter from FFFh to ATR value.
0: No counter overflow occurred
1: Counter overflow occurred
Caution:
When set, the OVF bit stays high for 1 f
cycle, (up to 1ms depending on the clock selec-
tion).
Bit 1 = OVFIE Overflow Interrupt Enable.
This bit is read/write by software and cleared by
hardware after a reset.
0: OVF interrupt disabled
1: OVF interrupt enabled
Bit 0 = CMPIE Compare Interrupt Enable.
This bit is read/write by software and clear by
56/124
1
7
0
f
LTIMER
Counter Clock Selection
0
(1 ms timebase @ 8 MHz)
Reserved
0
OFF
f
CPU
CK1
CK0
OVF
CK1
OVFIE CMPIE
0
0
1
1
COUNTER
CK0
0
1
0
1
0
hardware after a reset. It allows to mask the inter-
rupt generation when CMPF bit is set.
0: CMPF interrupt disabled
1: CMPF interrupt enabled
COUNTER REGISTER HIGH (CNTRH)
Read only
Reset Value: 0000 0000 (00h)
COUNTER REGISTER LOW (CNTRL)
Read only
Reset Value: 0000 0000 (00h)
Bits 15:12 = Reserved, must be kept cleared.
Bits 11:0 = CNTR[11:0] Counter Value.
This 12-bit register is read by software and cleared
by hardware after a reset. The counter is incre-
mented continuously as soon as a counter clock is
selected. To obtain the 12-bit value, software
should read the counter value in two consecutive
read operations. The CNTRH register can be in-
cremented between the two reads, and in order to
be accurate when f
should take this into account when CNTRL and
CNTRH are read. If CNTRL is close to its highest
value, CNTRH could be incremented before it is
read.
When a counter overflow occurs, the counter re-
starts from the value specified in the ATR register.
CN7
15
0
7
CN6
0
CN5
0
CN4
0
TIMER
CN11
CN3
=f
CPU
CN10
CN2
, the software
CN9
CN1
CN8
CN0
8
0