MCIMX535DVV1C Freescale Semiconductor, MCIMX535DVV1C Datasheet - Page 107
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MCIMX535DVV1C
Manufacturer Part Number
MCIMX535DVV1C
Description
IMX53 REV 2.1 COMM
Manufacturer
Freescale Semiconductor
Specifications of MCIMX535DVV1C
Rohs Compliant
YES
Core Size
32bit
Program Memory Size
288KB
Cpu Speed
1GHz
Digital Ic Case Style
BGA
No. Of Pins
529
Supply Voltage Range
1.25V To 1.35V
Operating Temperature Range
-20°C To +85°C
Msl
MSL 3 - 168 Hours
Embedded Interface Type
I2C, SPI, UART
Lead Free Status / Rohs Status
Supplier Unconfirmed
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4.7.9
The LVDS interface complies with TIA/EIA 644-A standard. For more details, see TIA/EIA STANDARD
644-A, “Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits”.
4.7.10
Figure 58
Freescale Semiconductor
7
DISP_DOWN is predefined in REGISTER.
8
DISP_UP is predefined in REGISTER.
1
Display control down for read
Display control up for write
OW1
OW2
OW3
OW4
In order not to mask signaling by other devices on the 1-Wire bus, t
One-Wire bus
(BATT_LINE)
ID
depicts the RPP timing, and
LVDS Display Bridge (LDB) Module Parameters
One-Wire (OWIRE) Timing Parameters
Reset Time Low
Presence Detect High
Presence Detect Low
Reset Time High
(includes recovery time)
Table 66. RPP Sequence Delay Comparisons Timing Parameters
Figure 58. Reset and Presence Pulses (RPP) Timing Diagram
i.MX53xD Applications Processors for Consumer Products, Rev. 3
Parameters
One-WIRE Tx
“Reset Pulse”
Tdicdrw
Tdicuw
OW1
=
Table 66
=
1
-- - T DI_CLK
2
1
-- - T DI_CLK
2
⎛
⎝
⎛
⎝
t
R
lists the RPP timing parameters.
Symbol
×
t
t
×
t
t
RSTH
RSTL
PDH
PDL
ceil
ceil
2
------------------------------------------------- -
--------------------------------------------- -
DI_CLK_PERIOD
DI_CLK_PERIOD
2
×
RSTL
×
DISP_DOWN_#
DISP_UP_#
OW3
+ t
OW2
One Wire Device Tx
Min
480
480
15
60
R
“Presence Pulse”
should always be less than 960 µs.
⎞
⎠
⎞
⎠
Typ
511
512
OW4
—
—
Electrical Characteristics
Max
240
—
60
—
1
Unit
µs
µs
µs
µs
107
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