MCIMX535DVV1C Freescale Semiconductor, MCIMX535DVV1C Datasheet - Page 26
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MCIMX535DVV1C
Manufacturer Part Number
MCIMX535DVV1C
Description
IMX53 REV 2.1 COMM
Manufacturer
Freescale Semiconductor
Specifications of MCIMX535DVV1C
Rohs Compliant
YES
Core Size
32bit
Program Memory Size
288KB
Cpu Speed
1GHz
Digital Ic Case Style
BGA
No. Of Pins
529
Supply Voltage Range
1.25V To 1.35V
Operating Temperature Range
-20°C To +85°C
Msl
MSL 3 - 168 Hours
Embedded Interface Type
I2C, SPI, UART
Lead Free Status / Rohs Status
Supplier Unconfirmed
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Electrical Characteristics
26
•IO Supplies (NVCC_xxx) below or equal to 2.8 V nom./3.1 V max. should not precede
•IO Supplies (NVCC_xxx) above 2.8 V nom./3.1 V max. should be powered ON only after
•In case VDD_DIG_PLL and VDD_ANA_PLL are powered ON from internal voltage regulator
•VDD_REG supply is required to be powered ON to enable DDR operation. It must be powered
•NVCC_EIM_DRAM_2P5 PoP additional power line timing is the same as DVV_REG
•VDDA and VDDAL1 can be powered ON anytime before POR_B, regardless of any other power
•VDDGP can be powered ON anytime before POR_B, regardless of any other power signal.
•VP and VPH can be powered up together, or anytime after, the VCC. VP and VPH should come
•TVDAC_DHVDD and TVDAC_AHVDDRGB should be powered from the same regulator. This
NVCC_CKIH. They can start powering ON during NVCC_CKIH ramp-up, before it is
stabilized. Within this group, the supplies can be powered-up in any order.
NVCC_CKIH is stable.
(default case for i.MX53xD), there are no related restrictions on VDD_REG, as it is used as their
internal regulators power source.
If VDD_DIG_PLL and VDD_ANA_PLL are powered on externally, to reduce current leakage
during the power-up, it is recommended to activate the VDD_REG before or at the same time
with VDD_DIG_PLL and VDD_ANA_PLL. If this sequencing is not possible, make sure that
the 2.5 V VDD_REG supply shut-off output impedance is higher than 1 kΩ when it is inactive.
on after VCC and before NVCC_EMI_DRAM. The sequence should be:
signal.
before POR.
is due to ESD diode protection circuit, that may cause current leakage if one of the supplies is
powered ON before the other.
The POR_B input must be immediately asserted at power-up and remain
asserted until after the last power rail reaches its working voltage.
i.MX53xD Applications Processors for Consumer Products, Rev. 3
VCC →VDD_REG →NVCC_EMI_DRAM
NOTE
Freescale Semiconductor
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