MCIMX535DVV1C Freescale Semiconductor, MCIMX535DVV1C Datasheet - Page 49
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MCIMX535DVV1C
Manufacturer Part Number
MCIMX535DVV1C
Description
IMX53 REV 2.1 COMM
Manufacturer
Freescale Semiconductor
Specifications of MCIMX535DVV1C
Rohs Compliant
YES
Core Size
32bit
Program Memory Size
288KB
Cpu Speed
1GHz
Digital Ic Case Style
BGA
No. Of Pins
529
Supply Voltage Range
1.25V To 1.35V
Operating Temperature Range
-20°C To +85°C
Msl
MSL 3 - 168 Hours
Embedded Interface Type
I2C, SPI, UART
Lead Free Status / Rohs Status
Supplier Unconfirmed
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Freescale Semiconductor
Lower frequency operation can be supported for most available devices in
the market, relying on data lines Bus-Keeper logic. This depends on device
behavior on the data bus in the time interval between data output valid to
data output high-Z state. In NAND device parameters this period is marked
between t
data transition from valid value to high-Z occurs without going through
other states. Setting the data bus pads to Bus-Keeper mode in the IOMUXC
registers, keeps the data bus valid internally after the specified hold time,
allowing proper capturing with slower clock.
NFCE_B
NFWE_B
NFALE
NFIO[7:0]
NFCLE
NFCE_B
NFWE_B
NFIO[7:0]
i.MX53xD Applications Processors for Consumer Products, Rev. 3
rhoh
and t
Figure 10. Command Latch Cycle Timing
Figure 11. Address Latch Cycle Timing
rhz
NF6
(RE_B high to output high-Z). In most devices, the
NF1
NF3
NF3
NF8
Address
NF5
command
NF8
NF5
NF10
NF7
NF4
NF9
NF9
NF11
NF2
NF4
Electrical Characteristics
49
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