MCIMX535DVV1C Freescale Semiconductor, MCIMX535DVV1C Datasheet - Page 93
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MCIMX535DVV1C
Manufacturer Part Number
MCIMX535DVV1C
Description
IMX53 REV 2.1 COMM
Manufacturer
Freescale Semiconductor
Specifications of MCIMX535DVV1C
Rohs Compliant
YES
Core Size
32bit
Program Memory Size
288KB
Cpu Speed
1GHz
Digital Ic Case Style
BGA
No. Of Pins
529
Supply Voltage Range
1.25V To 1.35V
Operating Temperature Range
-20°C To +85°C
Msl
MSL 3 - 168 Hours
Embedded Interface Type
I2C, SPI, UART
Lead Free Status / Rohs Status
Supplier Unconfirmed
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Table 61
Freescale Semiconductor
IP6
IP7
IP8
IP9
IP10
IP12
IP13
IP14
IP15
IP5
ID
Display interface clock period
Display pixel clock period
Screen width time
HSYNC width time
Horizontal blank interval 1
Horizontal blank interval 2
Screen height
VSYNC width
Vertical blank interval 1
Vertical blank interval 2
shows timing characteristics of signals presented in
Table 61. Synchronous Display Interface Timing Characteristics (Pixel Level)
Parameter
i.MX53xD Applications Processors for Consumer Products, Rev. 3
Symbol
Tdpcp
Thbi1
Thbi2
Tdicp
Tvbi1
Tvbi2
Thsw
Tvsw
Tsw
Tsh
DISP_CLK_PER_PIXEL
(SCREEN_HEIGHT –
BGXP – FW)
(SCREEN_WIDTH –
(SCREEN_HEIGHT)
(SCREEN_WIDTH)
BGYP – FH)
(HSYNC_WIDTH)
VSYNC_WIDTH
BGXP
BGYP
×
×
×
Value
Tdicp
Tdicp
(
Tsw
1
×
)
×
Tdicp
Tsw
×
×
Tdicp
Tsw
Figure 48
Display interface clock.
Time of translation of one pixel to display,
DISP_CLK_PER_PIXEL—number of pixel
components in one pixel (1.n). The
DISP_CLK_PER_PIXEL is virtual
parameter to define Display pixel clock
period.
The DISP_CLK_PER_PIXEL is received by
DC/DI one access division to n
components.
SCREEN_WIDTH—screen width in,
interface clocks. horizontal blanking
included.
The SCREEN_WIDTH should be built by
suitable DI’s counter
HSYNC_WIDTH—Hsync width in DI_CLK
with 0.5 DI_CLK resolution. Defined by DI’s
counter.
BGXP—width of a horizontal blanking
before a first active data in a line (in
interface clocks). The BGXP should be built
by suitable DI’s counter.
Width a horizontal blanking after a last
active data in a line (in interface clocks)
FW—with of active line in interface clocks.
The FW should be built by suitable DI’s
counter.
SCREEN_HEIGHT— screen height in lines
with blanking.
The SCREEN_HEIGHT is a distance
between 2 VSYNCs.
The SCREEN_HEIGHT should be built by
suitable DI’s counter.
VSYNC_WIDTH—Vsync width in DI_CLK
with 0.5 DI_CLK resolution. Defined by DI’s
counter
BGYP—width of first Vertical
blanking interval in line.The BGYP should
be built by suitable DI’s counter.
Width of second Vertical
blanking interval in line.The FH should be
built by suitable DI’s counter.
and
Figure
Description
2
.
Electrical Characteristics
IPP_DISP_CLK
49.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
93
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