LH75411N0Q100C0 NXP Semiconductors, LH75411N0Q100C0 Datasheet - Page 30

• Manufacturer Part Number: LH75411N0Q100C0
• Description: MCU ARM7, LCD CTRL, SMD, LQFP144
• Manufacturer: NXP Semiconductors

Specifications of LH75411N0Q100C0

• Core Size: 32bit
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 84MHz
• Oscillator Type: External Only
• No. Of Timers: 3
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 1.7V To 1.98V, 3V To 3.6V
• Controller Family/series: LH75xxx
• Peripherals: ADC, RTC, LVD
• Rohs Compliant: Yes
• Data Bus Width: 32 bit
• Program Memory Type: ROMLess
• Data Ram Size: 32 KB
• Interface Type: JTAG, SCI, SPI, SSI, UART
• Maximum Clock Frequency: 84 MHz
• Number Of Programmable I/os: 76
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LH75401/LH75411
Watchdog Timer (WDT)
allows a selectable time-out interval to detect malfunc-
tions. The timer must be reset by software periodically.
Otherwise, a time-out occurs, interrupting the system.
If the interrupt is not serviced within the timeout period,
the WDT triggers the RCPC to generate a System
Reset. If the WDT times out, it sets a bit in the RCPC
Reset Status Register.
a time-out of 216 through 231 system clock cycles. All
Control and Status Registers for the Watchdog Timer
are accessed through the APB.
30
Motorola SPI
SSI
National Semiconductor
Microwire
The WDT consists of a 32-bit down-counter that
The WDT supports 16 selectable time intervals, for
MODE
For communications with Motorola SPI-compatible
devices. Clock polarity and phase are programmable.
For communications with Texas Instruments DSP-
compatible Serial Synchronous Interface devices.
For communications with National Semiconductor
Microwire-compatible devices.
NXP Semiconductors
Rev. 01 — 16 July 2007
Table 10. SSP Modes
DESCRIPTION
WDT FEATURES
• Counter generates an interrupt at a set interval and
• Default timeout period is set to the minimum timeout
• WDT is driven by the APB.
• Built-in protection mechanism guards against
• WDT can be programmed to trigger a System Reset
• WDT can be programmed to trigger an interrupt on
the count reloads from the pre-set value after reach-
ing zero.
of 216 system clock cycles.
interrupt-service failure.
on a timeout.
the first timeout; then, if the service routine fails to
clear the interrupt, the next WDT timeout triggers a
System Reset.
Full-duplex, 4-wire
synchronous
Full-duplex, 4-wire
synchronous
Half-duplex synchronous, using
8-bit control messages
DATA TRANSFERS
Preliminary data sheet
System-on-Chip