PIC18F2320-E/SO Microchip Technology, PIC18F2320-E/SO Datasheet - Page 113

• Manufacturer Part Number: PIC18F2320-E/SO
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SOP,28PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2320-E/SO

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.5
PORTE is available only in PIC18F4X20 devices.
PIC18F2X20 devices always will read back 0x00 from
PORTE.
For PIC18F4X20 devices, PORTE is a 4-bit wide port.
Three pins (RE0/AN5/RD, RE1/AN6/WR and RE2/
AN7/CS) are individually configurable as inputs or out-
puts. These pins have Schmitt Trigger input buffers.
When selected as an analog input, these pins will read
as ‘0’s.
The corresponding Data Direction register is TRISE.
Setting a TRISE bit (= 1) will make the corresponding
PORTE pin an input (i.e., put the corresponding output
driver in a high-impedance mode). Clearing a TRISE bit
(= 0) will make the corresponding PORTE pin an output
(i.e., put the contents of the output latch on the selected
pin).
TRISE controls the direction of the RE pins even when
they are being used as analog inputs. The user must
make sure to keep the pins configured as inputs when
using them as analog inputs.
The upper four bits of the TRISE register also control
the operation of the Parallel Slave Port. Their operation
is explained in Register 10-1.
The Data Latch register (LATE) is also memory
mapped. Read-modify-write operations on the LATE
register read and write the latched output value for
PORTE.
The fourth pin of PORTE (MCLR/V
only pin. Its operation is controlled by the MCLRE Con-
figuration
(CONFIG3H<7>). When selected as a port pin
(MCLRE = 0), it functions as a digital input only pin; as
such, it does not have TRIS or LAT bits associated with
its operation. Otherwise, it functions as the device’s
Master Clear input. In either configuration, RE3 also
functions as the programming voltage input during
programming.
© 2007 Microchip Technology Inc.
Note:
Note:
PORTE, TRISE and LATE
Registers
On a Power-on Reset, RE2:RE0 are
configured as analog inputs.
On a Power-on Reset, RE3 is enabled as
a digital input only if Master Clear
functionality is disabled.
bit
in
Configuration
PP
/RE3) is an input
Register
PIC18F2220/2320/4220/4320
3H
EXAMPLE 10-5:
FIGURE 10-13:
CLRF
CLRF
MOVLW
MOVWF
MOVLW
MOVWF
Note 1:
RD LATE
Data
Bus
WR LATE
or
PORTE
WR TRISE
RD TRISE
To Analog Converter
RD PORTE
PORTE
LATE
0x0A
ADCON1 ; for digital inputs
0x03
TRISC
I/O pins have diode protection to V
TRIS Latch
Data Latch
D
D
CK
CK
; Initialize PORTE by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Configure A/D
; Value used to
; initialize data
; direction
; Set RE<0> as inputs
; RE<1> as outputs
; RE<2> as inputs
Q
Q
INITIALIZING PORTE
BLOCK DIAGRAM OF
RE2:RE0 PINS
Q
EN
EN
D
DS39599G-page 111
Schmitt
Trigger
Input
Buffer
DD
and V
SS
I/O pin
.
(1)