PIC18F2320-E/SO Microchip Technology, PIC18F2320-E/SO Datasheet - Page 140

• Manufacturer Part Number: PIC18F2320-E/SO
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SOP,28PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2320-E/SO

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F2220/2320/4220/4320
15.5
In Pulse Width Modulation (PWM) mode, the CCP1 pin
produces up to a 10-bit resolution PWM output. Since
the CCP1 pin is multiplexed with the PORTC data latch,
the TRISC<2> bit must be cleared to make the CCP1
pin an output.
Figure 15-3 shows a simplified block diagram of the
CCP module in PWM mode.
For a step-by-step procedure on how to set up the CCP
module for PWM operation, see Section 15.5.3
“Setup for PWM Operation”.
FIGURE 15-3:
A PWM output (Figure 15-4) has a time base (period)
and a time that the output is high (duty cycle). The
frequency of the PWM is the inverse of the period
(1/period).
FIGURE 15-4:
DS39599G-page 138
Note: 8-bit timer is concatenated with 2-bit internal Q clock or
CCPR1H (Slave)
Note:
Duty Cycle Registers
Comparator
CCPR1L
TMR2
TMR2 = PR2
PR2
2 bits of the prescaler to create 10-bit time base.
Comparator
PWM Mode
Duty Cycle
Clearing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is not the PORTC I/O data
latch.
(Note 1)
Period
Clear Timer,
CCP1 pin and
latch D.C.
TMR2 = Duty Cycle
SIMPLIFIED PWM BLOCK
DIAGRAM
PWM OUTPUT
CCP1CON<5:4>
TMR2 = PR2
R
S
Q
TRISC<2>
RC2/CCP1/P1A
15.5.1
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
following equation.
EQUATION 15-1:
PWM frequency is defined as 1/[PWM period]. When
TMR2 is equal to PR2, the following three events occur
on the next increment cycle:
• TMR2 is cleared
• The CCP1 pin is set (if PWM duty cycle = 0%, the
• The PWM duty cycle is copied from CCPR1L into
15.5.2
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available. The CCPR1L contains
the eight MSbs and the CCP1CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The PWM duty cycle is
calculated by the following equation.
EQUATION 15-2:
CCPR1L and CCP1CON<5:4> can be written to at any
time but the duty cycle value is not copied into
CCPR1H until a match between PR2 and TMR2 occurs
(i.e., the period is complete). In PWM mode, CCPR1H
is a read-only register.
CCP1 pin will not be set)
CCPR1H
Note:
PWM Duty Cycle = (CCPR1L:CCP1CON<5:4>) •
PWM Period = [(PR2) + 1] • 4 • T
PWM PERIOD
The Timer2 postscaler (see Section 13.0
“Timer2 Module”) is not used in the
determination of the PWM frequency. The
postscaler could be used to have a servo
update rate at a different frequency than
the PWM output.
PWM DUTY CYCLE
© 2007 Microchip Technology Inc.
T
(TMR2 Prescale Value)
OSC
• (TMR2 Prescale Value)
OSC
•