PIC18F2320-E/SO Microchip Technology, PIC18F2320-E/SO Datasheet - Page 115

• Manufacturer Part Number: PIC18F2320-E/SO
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SOP,28PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2320-E/SO

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TABLE 10-9:
TABLE 10-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
© 2007 Microchip Technology Inc.
PORTE
LATE
TRISE
ADCON1
Legend:
Note 1:
RE0/AN5/RD
RE1/AN6/WR
RE2/AN7/CS
MCLR/V
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1:
Name
Name
2:
PP
x = unknown, u = unchanged, - = unimplemented, read as ‘0’, q = value depends on condition.
Shaded cells are not used by PORTE.
The RE3 port bit is available as an input-only pin only in 40-pin devices and when Master Clear functionality is disabled
(CONFIG3H<7>=0).
/RE3
Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode.
The RE3 port bit is available as an input-only pin only in 40-pin devices and when Master Clear function-
ality is disabled (CONFIG3H<7>=0).
Bit 7
IBF
—
—
—
(2)
PORTE FUNCTIONS
Bit#
bit 0
bit 1
bit 2
bit 3
Bit 6
OBF
—
—
—
Buffer Type
VCFG1
ST/TTL
ST/TTL
ST/TTL
IBOV
Bit 5
—
—
ST
(1)
(1)
(1)
PSPMODE
VCFG0
Bit 4
—
—
PIC18F2220/2320/4220/4320
Input/output port pin, analog input or read control input in Parallel Slave
Port mode.
For RD (PSP Control mode):
1 = PSP is Idle
0 = Read operation. Reads PORTD register (if chip selected).
Input/output port pin, analog input or write control input in Parallel
Slave Port mode.
For WR (PSP Control mode):
1 = PSP is Idle
0 = Write operation. Writes PORTD register (if chip selected).
Input/output port pin, analog input or chip select control input in Parallel
Slave Port mode.
For CS (PSP Control mode):
1 = PSP is Idle
0 = External device is selected
Input only port pin or programming voltage input (if MCLR is disabled);
Master Clear input or programming voltage input (if MCLR is enabled).
PCFG3
RE3
Bit 3
—
—
(1)
LATE Data Latch Register
PORTE Data Direction bits
PCFG2
Bit 2
RE2
PCFG1
Bit 1
RE1
Function
PCFG0
Bit 0
RE0
---- qxxx
---- -xxx
0000 -111
--00 0000
POR, BOR
Value on
DS39599G-page 113
---- quuu
---- -uuu
0000 -111
--00 0000
Value on
all other
Resets