PIC18F4585-E/ML Microchip Technology, PIC18F4585-E/ML Datasheet - Page 246

• Manufacturer Part Number: PIC18F4585-E/ML
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,44PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4585-E/ML

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 48KB (24K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.25K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-QFN
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.25 KB
• Interface Type: I2C, SPI, EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 44
• Number Of Timers: 1 x 8
• Operating Supply Voltage: 4.2 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163011
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 11 bit
• Height: 0.88 mm
• Length: 8 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.2 V
• Width: 8 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: I3-DB18F4680 - BOARD DAUGHTER ICEPIC3
• Lead Free Status / Rohs Status: Details

PIC18F2585/2680/4585/4680
18.3.2
Once Synchronous mode is selected, reception is
enabled by setting either the Single Receive Enable bit,
SREN (RCSTA<5>), or the Continuous Receive
Enable bit, CREN (RCSTA<4>). Data is sampled on the
RX pin on the falling edge of the clock.
If enable bit SREN is set, only a single word is received.
If enable bit CREN is set, the reception is continuous
until CREN is cleared. If both bits are set, then CREN
takes precedence.
To set up a Synchronous Master Reception:
1.
2.
FIGURE 18-13:
TABLE 18-8:
DS39625C-page 244
INTCON
PIR1
PIE1
IPR1
RCSTA
RCREG
TXSTA
BAUDCON
SPBRGH
SPBRG
Legend:
Note 1:
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
Name
RC7/TX/CK pin
RC7/TX/CK pin
Initialize the SPBRGH:SPBRG registers for the
appropriate baud rate. Set or clear the BRG16
bit, as required, to achieve the desired baud rate.
Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
RC7/RX/DT
(SCKP = 0)
(SCKP = 1)
(Interrupt)
CREN bit
bit SREN
SREN bit
RCIF bit
RXREG
Write to
Read
— = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
Reserved in PIC18F2X8X devices; always maintain these bits clear.
EUSART SYNCHRONOUS
MASTER RECEPTION
EUSART Receive Register
EUSART Baud Rate Generator Register High Byte
EUSART Baud Rate Generator Register Low Byte
pin
GIE/GIEH
ABDOVF
PSPIF
PSPIE
PSPIP
Q2
CSRC
SPEN
Bit 7
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
‘0’
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
(1)
(1)
(1)
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
PEIE/GIEL
RCIDL
ADIF
ADIE
ADIP
Bit 6
RX9
TX9
bit 0
TMR0IE
SREN
TXEN
RCIE
RCIP
RCIF
Bit 5
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
—
bit 1
bit 2
INT0IE
CREN
SYNC
SCKP
Preliminary
TXIE
TXIP
Bit 4
TXIF
bit 3
ADDEN
SENDB
BRG16
SSPIF
SSPIE
SSPIP
RBIE
Bit 3
3.
4.
5.
6.
7.
8.
9.
10. If any error occurred, clear the error by clearing
11. If using interrupts, ensure that the GIE and PEIE
Ensure bits CREN and SREN are clear.
If interrupts are desired, set enable bit RCIE.
If 9-bit reception is desired, set bit RX9.
If a single reception is required, set bit SREN.
For continuous reception, set bit CREN.
Interrupt flag bit RCIF will be set when reception
is complete and an interrupt will be generated if
the enable bit RCIE was set.
Read the RCSTA register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG register.
bit CREN.
bits in the INTCON register (INTCON<7:6>) are
set.
bit 4
TMR0IF
CCP1IE
CCP1IP
CCP1IF
BRGH
FERR
Bit 2
—
bit 5
TMR2IF
TMR2IE
TMR2IP
INT0IF
OERR
TRMT
WUE
Bit 1
bit 6
© 2007 Microchip Technology Inc.
TMR1IE
TMR1IP
TMR1IF
ABDEN
RX9D
TX9D
RBIF
Bit 0
bit 7
Q1 Q2 Q3 Q4
Values on
Reset
page
49
52
52
52
51
51
51
51
51
51
‘0’