PIC18F4585-E/ML Microchip Technology, PIC18F4585-E/ML Datasheet - Page 470

• Manufacturer Part Number: PIC18F4585-E/ML
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,44PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4585-E/ML

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 48KB (24K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.25K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-QFN
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.25 KB
• Interface Type: I2C, SPI, EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 44
• Number Of Timers: 1 x 8
• Operating Supply Voltage: 4.2 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163011
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 11 bit
• Height: 0.88 mm
• Length: 8 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.2 V
• Width: 8 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: I3-DB18F4680 - BOARD DAUGHTER ICEPIC3
• Lead Free Status / Rohs Status: Details

PIC18F2585/2680/4585/4680
Equations
Errata ................................................................................... 5
Error Recognition Mode ................................................... 324
EUSART
Extended Instruction Set
External Clock Input ........................................................... 24
F
Fail-Safe Clock Monitor ............................................ 343, 355
Fast Register Stack ............................................................ 64
Firmware Instructions ....................................................... 361
Flash Program Memory ...................................................... 95
DS39625C-page 468
A/D
A/D Acquisition Time ................................................ 252
A/D Minimum Charging Time ................................... 252
Asynchronous Mode ................................................ 236
Baud Rate Generator (BRG)
Synchronous Master Mode ...................................... 242
Synchronous Slave Mode ........................................ 245
ADDFSR .................................................................. 404
ADDULNK ................................................................ 404
CALLW ..................................................................... 405
MOVSF .................................................................... 405
MOVSS .................................................................... 406
PUSHL ..................................................................... 406
SUBFSR .................................................................. 407
SUBULNK ................................................................ 407
Interrupts in Power Managed Modes ....................... 356
POR or Wake-up from Sleep ................................... 356
WDT During Oscillator Failure ................................. 355
Associated Registers ............................................... 103
Control Registers ....................................................... 96
Erase Sequence ...................................................... 100
Erasing ..................................................................... 100
Operation During Code-Protect ............................... 103
Reading ...................................................................... 99
Calculating the Minimum Required
Associated Registers, Receive ........................ 239
Associated Registers, Transmit ....................... 237
Auto-Wake-up on Sync Break .......................... 240
Break Character Sequence .............................. 241
Receiver ........................................................... 238
Setting up 9-Bit Mode with
Transmitter ....................................................... 236
Associated Registers ....................................... 231
Auto-Baud Rate Detect .................................... 234
Baud Rate Error, Calculating ........................... 231
Baud Rates, Asynchronous Modes .................. 232
High Baud Rate Select (BRGH Bit) .................. 231
Operation in Power Managed Mode ................ 231
Sampling .......................................................... 231
Associated Registers, Receive ........................ 244
Associated Registers, Transmit ....................... 243
Reception ......................................................... 244
Transmission .................................................... 242
Associated Registers, Receive ........................ 246
Associated Registers, Transmit ............... 245, 271
Reception ......................................................... 246
Transmission .................................................... 245
EECON1 and EECON2 ..................................... 96
TABLAT (Table Latch) Register ......................... 98
TBLPTR (Table Pointer) Register ...................... 98
Acquisition Time ...................................... 252
Address Detect ........................................ 238
Preliminary
FSCM. See Fail-Safe Clock Monitor.
G
GOTO .............................................................................. 382
H
Hardware Multiplier .......................................................... 111
High/Low-Voltage Detect ................................................. 267
HLVD. See High/Low-Voltage Detect.
I
I/O Ports ........................................................................... 129
I
2
C Mode (MSSP)
Table Pointer
Table Pointer Boundaries .......................................... 98
Table Reads and Table Writes .................................. 95
Write Sequence ....................................................... 101
Writing To ................................................................ 101
Introduction .............................................................. 111
Operation ................................................................. 111
Performance Comparison ........................................ 111
Characteristics ......................................................... 430
Effects of a Reset .................................................... 271
Operation ................................................................. 269
Typical Application ................................................... 270
Acknowledge Sequence Timing .............................. 220
Baud Rate Generator .............................................. 213
Bus Collision
Clock Arbitration ...................................................... 214
Clock Stretching ....................................................... 206
Clock Synchronization and the CKP bit
Effect of a Reset ...................................................... 221
General Call Address Support ................................. 210
I
Master Mode ............................................................ 211
Multi-Master Communication, Bus Collision
Multi-Master Mode ................................................... 221
Operation ................................................................. 200
Read/Write Bit Information (R/W Bit) ............... 200, 201
Registers ................................................................. 196
Serial Clock (RC3/SCK/SCL) ................................... 201
Slave Mode .............................................................. 200
2
C Clock Rate w/BRG ............................................. 213
Boundaries Based on Operation ....................... 98
Protection Against Spurious Writes ................. 103
Unexpected Termination ................................. 103
Write Verify ...................................................... 103
During Sleep .................................................... 271
Start-up Time ................................................... 269
During a Repeated Start Condition .................. 224
During a Stop Condition .................................. 225
10-Bit Slave Receive Mode (SEN = 1) ............ 206
10-Bit Slave Transmit Mode ............................ 206
7-Bit Slave Receive Mode (SEN = 1) .............. 206
7-Bit Slave Transmit Mode .............................. 206
(SEN = 1) ......................................................... 207
Operation ......................................................... 212
Reception ........................................................ 217
Repeated Start Condition Timing .................... 216
Start Condition ................................................. 215
Transmission ................................................... 217
Transmit Sequence ......................................... 212
and Arbitration ................................................. 221
Addressing ....................................................... 200
Reception ........................................................ 201
Transmission ................................................... 201
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