IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 75

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 6: PCI Express PHY (PIPE) IP Core
Interfaces
Figure 6–4. Rate Switch from Gen1 to Gen2
Note to
(1) Time T1 is pending characterization.
(2) <n> is the number of lanes.
Table 6–9. Transceiver Differential Serial Interface
Table 6–10. Status Signals
December 2010 Altera Corporation
pipe_phystatus[<n>-1:0]
rx_serial_data[<n>-1:0]
tx_serial_data[<n>-1:0]
tx_ready
rx_ready
pll_locked[<p>-1:0]
rx_is_lockedtodata[<n>-1:0]
rx_is_lockedtoref[<n>-1:0]
rx_syncstatus[<d><n>/8-1:0]
Note to
(1) <n> is the number of lanes. <d> is the deserialization factor. <p> is the number of PLLs.
Figure
Table
Transceiver Serial Interface
pipe_pclk
pipe_rate
Signal Name
Signal Name
6–4:
6–10:
Figure 6–4
Table 6–9
Table 6–10
(Note 1)
describes the differential serial TX and RX connections to FPGA pins.
illustrates the pipe_pclk switching from Gen1 to Gen2 and back to Gen1.
describes the signals the optional status signals.
Direction
Direction
Output
Output
Output
Output
Output
Output
Output
250 MHz (Gen1)
Input
T1
When asserted, indicates that the TX interface is ready to transmit.
When asserted, indicates that the RX interface is ready to receive.
When asserted, indicates that the PLL is locked to the input reference
clock. This signal is asynchronous.
When asserted, the receiver CDR is in to lock-to-data mode. When
deasserted, the receiver CDR lock mode depends on the
rx_locktorefclk signal level.
Asserted when the receiver CDR is locked to the input reference clock.
This signal is asynchronous.
Indicates presence or absence of synchronization on the RX interface.
Asserted when word aligner identifies the word alignment pattern or
synchronization code groups in the received data stream.
Receiver differential serial input data, <n> is the number of lanes.
Transmitter differential serial output data <n> is the number of lanes.
500 MHz (Gen2)
Signal Name
Description
T1
Altera Transceiver PHY IP Core User Guide
250 MHz (Gen1)
6–11