IP-ASI Altera, IP-ASI Datasheet
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... Asynchronous Serial Interface (ASI) MegaCore Function User Guide Asynchronous Serial Interface (ASI) MegaCore Function 101 Innovation Drive San Jose, CA 95134 www.altera.com UG-ASI0106-10.1 Document last updated for Altera Complete Design Suite version: Document publication date: User Guide 10.1 January 2011 Subscribe ...
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... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ...
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... Simulate the System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3 MegaWizard Plug-In Manager Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3 Specify Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4 Simulate the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5 Simulate with IP Functional Simulation Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5 Simulate with the ModelSim Simulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6 Simulating in Third-Party Simulation Tools Using NativeLink . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6 Compile the Design and Program a Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7 Chapter 3 ...
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... Constrain Design With TimeQuest Timing Analyzer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–1 Specify Clock Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–2 Define the Setup and Hold Relationship between the 135-MHz Clocks and the 337.5-MHz zero-degree Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–2 Specify Clocks that are Exclusive or Asynchronous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–3 Minimize Timing Skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–3 Constraints For ASI Receivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–4 Non-Cyclone Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A– ...
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... January 2011 Altera Corporation 1. About This MegaCore Function Item MegaCore IP Library Release Notes Asynchronous Serial Interface (ASI) MegaCore Function User Guide ® function implements a Description 10.1 January 2011 IP-ASI 00B9 6AF7 MegaCore IP Library Release Notes ® II software compiles the ...
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... EP4CGX30F484 pin package) devices. (4) Stratix IV GT only supports soft logic mode. Features This section summarizes the features of the ASI MegaCore function. ■ IP functional simulation models for use in Altera-supported VHDL and Verilog HDL simulators ■ Easy-to-use MegaWizard ■ SOPC Builder ready Support for OpenCore Plus evaluation ■ ...
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... The ASI MegaCore verification involves the testing of the DVB-ASI specification EN 50083-9 from CENELEC / December 2002 “Cable networks for television signals, sound signals and interactive services. Part 9: Interfaces for CATV/SMATV head-ends and similar professional equipment for DVB/MPEG2 transport streams”. Resource Utilization Table 1–3 shows estimated resource usage for the ASI MegaCore function, with the Quartus II software version 10 ...
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... Installation and Licensing The ASI MegaCore function is part of the MegaCore IP Library, which is distributed with the Quartus II software and downloadable from the Altera website, www.altera.com. f For system requirements and installation instructions, refer to Installation & Figure 1–1 on page 1–4 MegaCore function, where <path> is the installation directory. The default installation directory on Windows is c:\altera\< ...
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... Chapter 1: About This MegaCore Function Installation and Licensing OpenCore Plus Evaluation With Altera’s free OpenCore Plus evaluation feature, you can perform the following actions: ■ Simulate the behavior of a megafunction (Altera MegaCore function or AMPP megafunction) within your system ■ Verify the functionality of your design, as well as evaluate its size and speed ...
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... Asynchronous Serial Interface (ASI) MegaCore Function User Guide Chapter 1: About This MegaCore Function Installation and Licensing January 2011 Altera Corporation ...
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... Select Flow You can parameterize the ASI MegaCore function using either one of the following flows: SOPC Builder flow ■ ■ MegaWizard Plug-In Manager flow January 2011 Altera Corporation Select Design Flow MegaWizard Plug-In Manager Flow Specify Parameters Simulate with Testbench Instantiate Core ...
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... DMA controller Use the accompanying Nios II/Interniche ■ TCP/IP protocol stack software driver support in your system SOPC Builder Flow The SOPC Builder flow allows you to add the ASI MegaCore function directly to a new or existing SOPC Builder system. You can also easily add other available components to quickly create an SOPC Builder system with an ASI, such as the Nios II processor, external memory controllers and scatter/gather DMA controllers ...
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... You can alternatively use the IP Advisor to help you start your ASI MegaCore design. On the Quartus II Tools menu, point to Advisors, and then click IP Advisor. The IP Advisor guides you through a series of recommendations for selecting, parameterizing, evaluating, and instantiating an ASI MegaCore function into your design ...
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... Specify the parameters on all pages in the Parameter Settings tab. f For detailed explanation of the parameters, refer to the Settings” on page 4. On the EDA tab, turn on Generate simulation model to generate an IP functional simulation model for the MegaCore function functional simulation model is a cycle-accurate VHDL or Verilog HDL model produced by the Quartus II software. ...
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... This XML file describes the MegaCore pin attributes to the Quartus II Pin Planner. MegaCore pin attributes include pin direction, location, I/O standard assignments, and drive strength. If you launch IP Toolbench outside of the Pin Planner application, you must explicitly load this file to use Pin Planner. ...
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... Simulation Tools Altera provides a Quartus II project for use with NativeLink in the ip\asi\simulation\quartus directory. To set up simulation in the Quartus II software using NativeLink, follow these steps the File menu click Open Project. Browse to the ip\asi\simulation\quartus directory. 2. Open asi_sim.qpf. 3. Set up the Quartus II NativeLink the Assignments menu, click Settings. ...
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... Compile the Design and Program a Device You can use the Quartus II software to compile your design. Refer to Quartus II Help for instructions on performing compilation. After you have compiled your design, program your targeted Altera device and verify your design in hardware. January 2011 Altera Corporation Asynchronous Serial Interface (ASI) MegaCore Function User Guide 2– ...
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... Asynchronous Serial Interface (ASI) MegaCore Function User Guide Chapter 2: Getting Started Compile the Design and Program a Device January 2011 Altera Corporation ...
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... For Stratix II GX, Stratix IV GX and Stratix GX devices, specify soft logic for the transceiver. When you turn on Use soft logic for transceiver, the transceiver is implemented in the device’s logic, otherwise the design uses a Stratix II GX, Stratix Stratix GX transceiver. Asynchronous Serial Interface (ASI) MegaCore Function User Guide Description ...
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... Asynchronous Serial Interface (ASI) MegaCore Function User Guide Chapter 3: Parameter Settings January 2011 Altera Corporation ...
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... Low voltage differential signalling (LVDS) inputs and outputs (I/Os) for the receiver and transmitter ■ ASI transmitter ■ ASI receiver Two PLLs for frequency multiplication—one for the transmitter, one for the ■ receiver Transmitter The transmitter comprises the following elements: ■ ...
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... LVDS output buffer is implemented for that function. You should use a PLL that multiplies a 27-MHz reference clock by ten to provide the bit-rate clock and enables jitter-controlled ASI transmit serialization. ...
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... The serial data stream from the LVDS input buffer is sampled using four different clocks phase-shifted by 90° from each other. Two out of these four clocks are created from an on-chip PLL. The two remaining clocks are created by inversion of the PLL clock outputs and should be 337.5-MHz clocks. ...
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... Asynchronous Serial Interface (ASI) MegaCore Function User Guide SYNC_REQ 1 ! CODE_ERROR and KCODE_FOUND SYNC_REQ 2 ! CODE_ERROR and KCODE_FOUND ! CODE_ERROR IN_SYNC 1 ! CODE_ERROR IN_SYNC 2 ! CODE_ERROR IN_SYNC 3 ! CODE_ERROR IN_SYNC 4 Chapter 4: Functional Description Receiver Figure 4–3 shows the CODE_ERROR January 2011 Altera Corporation ...
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... Chapter 4: Functional Description Testbench The block first looks for the synchronization byte that indicates the start of the packet, which is indicated by rx_ts_status[1]. The block then counts valid bytes in the incoming stream synchronization byte is seen 188 or 204 bytes after the first sync byte is seen, lock is indicated on rx_ts_[5:4] and end of packet is indicated on rx_ts_status[2] ...
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... Unlike rx_ts_status[0], this signal is not dependent on the correct packet or synchronization structure of the stream. Output from transmitter protocol block for split Output protocol/transceiver mode. Chapter 4: Functional Description Signals Description January 2011 Altera Corporation ...
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... Specify timing constraints and exceptions. To enter your timing requirements, you can use constraint entry dialog boxes or edit the previously created .sdc file. The following constraints demonstrates how to properly constrain the ASI MegaCore RX and TX targeting Stratix IV device. January 2011 Altera Corporation A. Constraints Asynchronous Serial Interface (ASI) MegaCore Function User Guide ...
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... Define the Setup and Hold Relationship between the 135-MHz Clocks and the 337.5-MHz zero-degree Clocks These constraints apply only to Soft Transceiver ASI. ■ ...
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... The following code is an example of a constraint, which you can set using the Quartus II Assignment Editor: set_location_assignment PIN_99 -to asi_rx0 set_location_assignment LC_X32_Y17_N0 -to "asi_rx:u_rx0|asi_megacore_top:asi_megacore_top_inst|asi_receive:asi rx_gen.u_rx|serdes_s2p:u_s2p|sample_a[0]" set_location_assignment LC_X33_Y17_N0 -to "asi_rx:u_rx0|asi_megacore_top:asi_megacore_top_inst|asi_receive:asi rx_gen.u_rx|serdes_s2p:u_s2p|sample_b[0]" set_location_assignment LC_X32_Y17_N1 -to "asi_rx:u_rx0|asi_megacore_top:asi_megacore_top_inst|asi_receive:asi rx_gen.u_rx|serdes_s2p:u_s2p|sample_c[0]" set_location_assignment LC_X33_Y17_N1 -to "asi_rx:u_rx0|asi_megacore_top:asi_megacore_top_inst|asi_receive:asi rx_gen.u_rx|serdes_s2p:u_s2p|sample_d[0]" January 2011 Altera Corporation Asynchronous Serial Interface (ASI) MegaCore Function User Guide A–3 ...
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... These constraints apply to all device families (excluding Cyclone, but including Cyclone II, Cyclone III, and Cyclone IV devices) that are configured to use a soft transceiver. Define the following setup and hold relationship between the 135-MHz clocks and the 337.5-MHz zero-degree clocks: ■ Setup—1.5 clocks (4.43 ns) from the 337.5-MHz zero degree clock to the 135-MHz clock ■ ...
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... IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL ON -to "u_rx_pll|c2" Classic Timing Analyzer Use the following constraints for the Classic timing analyzer: set_instance_assignment -name SETUP_RELATIONSHIP "4.43 ns" -from "u_rx_pll|c0" -to "u_rx_pll|c2" 1 Where 337.5-MHz PLL output and c2 is the 135-MHz PLL output. set_instance_assignment -name HOLD_RELATIONSHIP "0 ns" -from " ...
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... A–6 rxclk set_global_assignment -name ENABLE_CLOCK_LATENCY ON set_instance_assignment -name HOLD_RELATIONSHIP "0 ns" -from "u_rx_pll|altpll:altpll_component|_clk0" -to "u_clkdiv|clkdiv" set_instance_assignment -name SETUP_RELATIONSHIP "4.43 ns" -from "u_rx_pll|altpll:altpll_component|_clk0" -to "u_clkdiv|clkdiv" TimeQuest Timing Analyzer Use the following constraints for the TimeQuest timing analyzer: derive_pll_clocks -use_net_name create_clock -period "27 MHz" create_generated_clock -divide_by 5 -multiply_by 2 set_max_delay 4 ...
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... To locate the most up-to-date information about Altera products, refer to the following table. Contact Technical support Technical training Product literature Non-technical support (General) (Software Licensing) Note to Table: (1) You can also contact your local Altera sales office or sales representative. January 2011 Altera Corporation Additional Information Changes (1) Contact Method Website www.altera.com/support Website www ...
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... GUI. Indicates directory names, project names, disk drive names, file names, file name extensions, software utility names, and GUI labels. For example, \qdesigns directory, D: drive, and chiptrip.gdf file. Indicate document titles. For example, Stratix IV Design Guidelines. Indicates variables. For example ...