IP-ASI Altera, IP-ASI Datasheet - Page 30

• Manufacturer Part Number: IP-ASI
• Description: IP CORE - ASI Video Interface
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-ASI

• Software Application: IP CORE, Interface And Protocols, AUDIO AND VIDEO
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Receiver/Transmitter for Digital Video Broadcast
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

A–4
Figure A–1. Register Placement
Constraints For ASI Receivers
Asynchronous Serial Interface (ASI) MegaCore Function User Guide
Non-Cyclone Devices
Figure A–1
floorplan.
You must add constraints to receiver ASI MegaCore functions. There are constraints
specific only to Cyclone devices and there are other constraints that apply to the other
device families (including Cyclone II, Cyclone III, and Cyclone IV devices). There are
different constraints that apply to the Classic timing analyzer and the TimeQuest
timing analyzer.
These constraints apply to all device families (excluding Cyclone, but including
Cyclone II, Cyclone III, and Cyclone IV devices) that are configured to use a soft
transceiver.
Define the following setup and hold relationship between the 135-MHz clocks and the
337.5-MHz zero-degree clocks:
■
■
Setup—1.5 clocks (4.43 ns) from the 337.5-MHz zero degree clock to the 135-MHz
clock
Hold—zero clocks from the 337.5-MHz clock to the 135-MHz clock
shows the placement of these registers in the Quartus II chip planner
January 2011 Altera Corporation
Constraints For ASI Receivers
Appendix A: Constraints