IP-ASI Altera, IP-ASI Datasheet - Page 27

• Manufacturer Part Number: IP-ASI
• Description: IP CORE - ASI Video Interface
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-ASI

• Software Application: IP CORE, Interface And Protocols, AUDIO AND VIDEO
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Receiver/Transmitter for Digital Video Broadcast
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Introduction
Constrain Design With TimeQuest Timing Analyzer
January 2011 Altera Corporation
For the ASI MegaCore function to work reliably, you must implement the following
Quartus II constraints:
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To ensure your design meets timing and other requirements, you must constrain the
design. This section provides the necessary steps to properly constrain your ASI
design using TimeQuest timing analyzer.
1. Set up the Quartus II TimeQuest timing analyzer.
2. Perform initial compilation to create an initial design database before you specify
3. Run the Quartus II TimeQuest timing analyzer. On the Tools menu, click
4. Create timing netlist based on the fully annotated database from the post-fit
5. Write SDC constraint file. The Quartus II software does not automatically update
6. Specify timing constraints and exceptions. To enter your timing requirements, you
The following constraints demonstrates how to properly constrain the ASI MegaCore
RX and TX targeting Stratix IV device.
Specify clock characteristics
Set timing exceptions such as false path, minimum delay and maximum delay
Minimize the timing skew among the paths from I/O pins to the four sampling
registers
Set the oversampling clock that is used by the oversampling interface to 135 MHz
as an independent clock domain
a. To specify the Quartus II TimeQuest timing analyzer as the default timing
b. In the Settings dialog box, under the Category list, select Timing Analysis
c. Turn on Use TimeQuest Timing Analyzer during compilation option, and
timing constraints for your design. On the Processing menu, click Start
Compilation.
TimeQuest Timing Analyzer.
results, after you perform a full compilation. Double-click Create Timing Netlist
in the Tasks pane.
.sdc files. You must explicitly write new or update constraints in the TimeQuest
timing analyzer. On the Constraints menu, click Write SDC File to write your
constraints to an .sdc file.
can use constraint entry dialog boxes or edit the previously created .sdc file.
analyzer, on the Assignments menu, click Settings.
Settings.
click OK.
Asynchronous Serial Interface (ASI) MegaCore Function User Guide
A. Constraints