IP-ASI Altera, IP-ASI Datasheet - Page 32

• Manufacturer Part Number: IP-ASI
• Description: IP CORE - ASI Video Interface
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-ASI

• Software Application: IP CORE, Interface And Protocols, AUDIO AND VIDEO
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Receiver/Transmitter for Digital Video Broadcast
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

A–6
Asynchronous Serial Interface (ASI) MegaCore Function User Guide
rxclk
set_global_assignment -name ENABLE_CLOCK_LATENCY ON
set_instance_assignment -name HOLD_RELATIONSHIP "0 ns" -from
"u_rx_pll|altpll:altpll_component|_clk0" -to "u_clkdiv|clkdiv"
set_instance_assignment -name SETUP_RELATIONSHIP "4.43 ns" -from
"u_rx_pll|altpll:altpll_component|_clk0" -to "u_clkdiv|clkdiv"
TimeQuest Timing Analyzer
Use the following constraints for the TimeQuest timing analyzer:
derive_pll_clocks -use_net_name
create_clock -period "27 MHz"
create_generated_clock -divide_by 5 -multiply_by 2
set_max_delay 4.43 -from {u_rx_pll|altpll:altpll_component|_clk0} -to
{u_clkdiv|clkdiv}
set_min_delay 0 -from {u_rx_pll|altpll:altpll_component|_clk0} -to
{u_clkdiv|clkdiv}
-source u_rx_pll|altpll:altpll_component|_clk0 \
-name {u_clkdiv|clkdiv} \
-name {rx_refclk} {rx_refclk}
January 2011 Altera Corporation
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Constraints For ASI Receivers
Appendix A: Constraints