IP-ASI Altera, IP-ASI Datasheet - Page 22

• Manufacturer Part Number: IP-ASI
• Description: IP CORE - ASI Video Interface
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-ASI

• Software Application: IP CORE, Interface And Protocols, AUDIO AND VIDEO
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Receiver/Transmitter for Digital Video Broadcast
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

4–2
Receiver
Figure 4–2. ASI Receiver
Asynchronous Serial Interface (ASI) MegaCore Function User Guide
337.5-MHz
Transceiver
Clock
Deserializer
Transceiver
Serial Data
f
LVDS I/O
337.5-MHz
Clock -90
Serializer
The serializer converts a 10-bit parallel word into a serial data output format. A 10-bit
shift register loaded at the word rate from the encoder and unloaded at the bit rate of
the LVDS output buffer is implemented for that function. You should use a PLL that
multiplies a 27-MHz reference clock by ten to provide the bit-rate clock and enables
jitter-controlled ASI transmit serialization.
GX Transceivers
For GX-based devices, in the MegaWizard Plug-In Manager you can select either a
soft-logic transceiver or a GX transceiver. If you are using GX transceivers, the
transmitter has a FIFO buffer, oversampler, and a transceiver, which replace the
soft-logic serializer.
For more information on the Stratix IV transceiver, refer to the
Handbook; for more information on the Stratix II GX transceiver, refer to the
Stratix II GX Device
refer to the
The receiver comprises the following elements:
■
■
■
■
■
Figure 4–2
The transceiver can be either a deserializer for soft-logic implementations or a GX
transceiver.
Transceiver
10
o
Deserializer
Oversampling Interface
Word Aligner
8B10B Decoder
Synchronization State Machine
Oversampling
135 MHz
shows the ASI receiver.
Interface
Stratix GX Device
Soft-logic transceiver implementations only
GX-based devices only
Clock
Handbook; and for more information on the Stratix GX transceiver,
10
Aligner
Word
Handbook.
10
Protocol Blocks
Decoder
8B10B
8
Sync.
FSM
Chapter 4: Functional Description
January 2011 Altera Corporation
Stratix IV Device
Packet
Sync.
Parallel
Data
Out
Receiver