IP-SDRAM/HPDDR Altera, IP-SDRAM/HPDDR Datasheet - Page 37

• Manufacturer Part Number: IP-SDRAM/HPDDR
• Description: IP CORE - DDR SDRAM High Performance Controller
• Manufacturer: Altera

Specifications of IP-SDRAM/HPDDR

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Stratix FPGAs, Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 4: Functional Description
Block Description
© March 2009 Altera Corporation
f
For more information on the ECC registers, refer to
Description.
The ECC can instantiate multiple encoders, each running in parallel, to encode any
width of data words assuming they are integer multiples of 64.
The ECC operates between the local (native or Avalon-MM interface) and the
memory controller.
The ECC has an N × 64-bit (where N is an integer) wide interface, between the local
interface and the ECC, for receiving and returning data from the local interface. This
interface can be a native interface or an Avalon-MM slave interface, you select the
type of interface in the MegaWizard interface.
The ECC has a second interface between the local interface and the ECC, which is a
32-bit wide Avalon-MM slave to control and report the status of the operation of the
ECC controller.
The encoded data from the ECC is sent to the memory controller using a N × 72-bit
wide Avalon-MM master interface, which is between the ECC and the memory
controller.
When testing the DDR SDRAM high-performance controller, you can turn off the
ECC.
Interrupts
The ECC issues an interrupt signal when one of the following scenarios occurs:
■
■
The error counters increment every time the respective event occurs for all N parts of
the return data word. This incremented value is compared with the maximum
threshold and an interrupt signal is sent when the value is equal to the maximum
threshold. The ECC clears the interrupts when you write a 1 to the respective status
register. You can mask the interrupts from either of the counters using the control
word.
Partial Writes
The ECC supports partial writes. Along with the address, data, and burst signals, the
Avalon-MM interface also supports a signal vector that is responsible for byte-enable.
Every bit of this signal vector represents a byte on the data-bus. Thus, a 0 on any of
these bits is a signal for the controller not to write to that particular location—a partial
write.
■
The single-bit error counter reaches the set maximum single-bit error threshold
value.
The double-bit error counter reaches the set maximum double-bit error threshold
value.
Counters:
■
■
Detected and/or corrected single-bit errors
Detected double-bit errors
DDR and DDR2 SDRAM High-Performance Controller User Guide
Appendix A, ECC Register
4–9