IP-SDRAM/HPDDR Altera, IP-SDRAM/HPDDR Datasheet - Page 80

• Manufacturer Part Number: IP-SDRAM/HPDDR
• Description: IP CORE - DDR SDRAM High Performance Controller
• Manufacturer: Altera

Specifications of IP-SDRAM/HPDDR

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Stratix FPGAs, Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

5–8
DDR and DDR2 SDRAM High-Performance Controller User Guide
Figure 5–3 on page 5–9
and memory interfaces, together with the test complete signals.
As the data written to the memory is simply an LFSR pattern, the example driver is
able to generate expected read data from the memory to compare with that previously
written to the same address. The data on the read data bus should match that on the
write data bus during the read process.
shows the series of writes followed by reads on both the local
Chapter 5: Example Design Walkthrough
© March 2009 Altera Corporation
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