IP-SDRAM/HPDDR Altera, IP-SDRAM/HPDDR Datasheet - Page 46

• Manufacturer Part Number: IP-SDRAM/HPDDR
• Description: IP CORE - DDR SDRAM High Performance Controller
• Manufacturer: Altera

Specifications of IP-SDRAM/HPDDR

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Stratix FPGAs, Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

4–18
Figure 4–6. Full Rate Write, Native Interface Mode—Non-Consecutive Write
Note to
(1) DDR Command and Mem Command show the command that the command signals are issuing.
DDR and DDR2 SDRAM High-Performance Controller User Guide
control_wdata_val[0]
control_dqs_burst[0]
DDR Command (1)
Mem Command (1)
Controller-PHY Interface
PHY Memory Interface
local_wdata_req
local_write_req
local_address
control_wdata
mem_dqs[0]
local_wdata
ddr_cs_n[0]
mem_dm[0]
local_ready
Figure
mem_cs_n
mem_addr
control_be
Local Interface
local_size
mem_clk
mem_ba
mem_dq
local_be
phy_clk
ddr_ba
ddr_a
4–6:
0
(Non-AFI)
4
802 804 806 808
[1]
AA
[2]
BB CC
1
0
WR
08
0
[3]
DD EE
80A
[4]
FF GG
WR
8
AA BB
[5]
HH
00
II
A A B B
JJ
PCH
KK
00
LL
[6]
3
3
[7]
ACT
04
PCH
2
00
[8] [9]
000
WR
04
ACT
04
00
0
00
WR
08
[10]
Chapter 4: Functional Description
© March 2009 Altera Corporation
00
WR
04
WR
CC DD
0C
00
00
WR
[11]
08
WR
EE
10
Interfaces and Signals
00
00
FF
[12]
WR
0C
WR
GG
14
00 10
C C D D
HH
WR
[13]