IPR-SDRAM/HPDDR2 Altera, IPR-SDRAM/HPDDR2 Datasheet

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... DDR and DDR2 SDRAM High-Performance 101 Innovation Drive San Jose, CA 95134 www.altera.com Controller User Guide Software Version: Document Date: March 2009 9.0 ...

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... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation ...

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... Address and Command Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–4 PHY Interface Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–4 ODT Generation Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–4 Low Power Mode Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–4 Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–5 Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–5 Error Correction Coding (ECC 4–7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–9 © March 2009 Altera Corporation Contents DDR and DDR2 SDRAM High-Performance Controller User Guide ...

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... Functional Memory Use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–7 Appendix A. ECC Register Description ECC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–1 Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–3 Additional Information Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1 How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1 Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–2 DDR and DDR2 SDRAM High-Performance Controller User Guide © March 2009 Altera Corporation ...

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... Altera does not verify compilation with MegaCore function versions older than one release. Device Family Support MegaCore functions provide either full or preliminary support for target Altera device families, as described below: ■ Full support means the MegaCore function meets all functional and timing requirements for the device family and may be used in production designs ■ ...

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... Support for OpenCore Plus evaluation ■ ■ Support for the Quartus II IP Advisor ■ IP functional simulation models for use in Altera-supported VHDL and Verilog HDL simulators General Description The Altera DDR and DDR2 SDRAM High-Performance Controller MegaCore functions provide simplified interfaces to industry-standard DDR SDRAM and DDR2 SDRAM ...

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... Denali models to ensure the functionality of the DDR and DDR2 SDRAM high-performance controller. In addition, Altera performs a wide variety of gate-level tests of the DDR and DDR2 SDRAM high-performance controllers to verify the post-compilation functionality of the controllers. ...

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... Memory Dedicated Logic Registers M512 M4K 1,562 4 2 1,738 4 4 2,783 5 15 2,958 4 17 1,332 6 0 1,421 3 3 1,939 3 9 2,026 4 9 © March 2009 Altera Corporation ...

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... AFI mode (including ALTMEMPHY) for Stratix II and Stratix II GX devices. Table 1–6. Resource Utilization in Stratix II and Stratix II GX Devices Local Data Controller Rate Width (Bits) Half 32 64 256 288 Full 32 64 256 288 © March 2009 Altera Corporation Memory Width Combinational (Bits) ALUTs 8 2,683 16 2,905 64 4,224 72 4,478 8 2,386 16 ...

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... Chapter 1: About These MegaCore Functions Performance and Resource Utilization Dedicated Logic Memory Registers (M9K) 1,432 2 1,581 3 2,465 9 2,613 10 1,351 2 1,431 2 1,897 5 1,975 6 Dedicated Logic Memory Registers (M9K) 1,452 1 1,597 2 2,457 8 2,601 9 1,369 1 1,448 1 1,906 4 1,983 5 © March 2009 Altera Corporation ...

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... If you want to use the DDR or DDR2 SDRAM High-Performance Controller MegaCore function, you can request a license file from the Altera web site at www.altera.com/licensing license file, Altera emails you a license.dat file. If you do not have Internet access, contact your local Altera representative. OpenCore Plus Evaluation With Altera’ ...

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... Your design stops working after the hardware evaluation time expires and the local_ready output goes low. DDR and DDR2 SDRAM High-Performance Controller User Guide Chapter 1: About These MegaCore Functions Installation and Licensing AN320: OpenCore Plus Evaluation © March 2009 Altera Corporation ...

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... DDR and DDR2 SDRAM High-Performance Controller MegaCore function and the Quartus II software. The sections in this chapter describe each stage. Figure 2–1. Design Flow © March 2009 Altera Corporation Select Design Flow MegaWizard Plug-In Manager Flow ...

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... DDR and DDR2 SDRAM High-Performance Controller User Guide SOPC Builder Flow Design directly from the DDR or DDR2 ■ SDRAM interface to peripheral device or devices Achieves higher-frequency operation ■ Chapter 2: Getting Started Select Flow MegaWizard Plug-In Manager Flow volume 4 of the Quartus II © March 2009 Altera Corporation ...

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... If there are warnings about overlapping addresses, on the System menu, click Auto Assign Base Addresses. If you enable ECC and there are warnings about overlapping IRQs, on the System menu click Auto Assign IRQs. © March 2009 Altera Corporation 3–1. Table 2–2 for more Avalon-MM addresses for AFI ...

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... During system generation, SOPC Builder optionally generates a simulation model and testbench for the entire system, which you can use to easily simulate your system in any of Altera's supported simulation tools. SOPC Builder also generates a set of ModelSim Tcl scripts and macros that you can use to compile the testbench, IP ® ...

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... IP core. In most cases, the .qip file contains all of the necessary assignments and information required to process the MegaCore function or system in the Quartus II compiler. The MegaWizard interface generates a single .qip file for each MegaCore function. © March 2009 Altera Corporation 3–1. Table 2–3. ...

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... Includes a delay module for simulation. This file is only generated if you choose VHDL as the language of your MegaWizard Plug-In Manager output files. Generated file that contains DQ/DQS I/O atoms interconnects and instance. Arria II GX devices only. Chapter 2: Getting Started MegaWizard Plug-In Manager Flow Description © March 2009 Altera Corporation ...

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... March 2009 Altera Corporation Description Specification file that generates the <variation_name>_alt_mem_phy_dq_dqs file using the clearbox flow. Arria II GX devices only. Quartus II IP file for the PLL that your ALTMEMPHY variation uses that contains the files associated with this megafunction ...

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... VHDL or Verilog HDL testbench for your example design, which is in the testbench directory in your project directory. You can use the IP functional simulation model with any Altera-supported VHDL or Verilog HDL simulator. You can perform a simulation in a third-party simulation tool from within the Quartus II software, using NativeLink. ...

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... Chapter 5, Example Design IP Functional Simulations For VHDL simulations with IP functional simulation models, perform the following steps: 1. Create a directory in the <project directory>\testbench directory. © March 2009 Altera Corporation AN 328: Interfacing DDR2 Knowledge Database Walkthrough. DDR and DDR2 SDRAM High-Performance Controller User Guide 2– ...

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... ALTGXB (1) <device name>_mf.vhd <device name>_mf_components.vhd <device name>_hssi (1) <device name>_hssi_components.vhd <device name>_hssi_atoms.vhd DDR and DDR2 SDRAM High-Performance Controller User Guide Chapter 2: Getting Started MegaWizard Plug-In Manager Flow Table (1) © March 2009 Altera Corporation 2–4. ...

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... ALTGXB_ver ■ <device name>_hssi_ver ■ auk_ddr_hp_user_lib ■ 3. Compile the files into the appropriate library as shown in © March 2009 Altera Corporation (2) Table 2–5 on page DDR and DDR2 SDRAM High-Performance Controller User Guide 2–11 2–12. ...

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... NativeLink 4. Configure your simulator to use transport delays, a timestep of picoseconds, and to include all the libraries in DDR and DDR2 SDRAM High-Performance Controller User Guide MegaWizard Plug-In Manager Flow (1) Table 2–5. © March 2009 Altera Corporation Chapter 2: Getting Started (2) ...

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... Browse to your SOPC Builder system top-level design or <variation name>_example_top if you are using MegaWizard Plug-In Manager, and click Open the Project menu, click Set as Top-Level Entity. © March 2009 Altera Corporation <your instance name> DDR and DDR2 SDRAM High-Performance Controller User Guide 2–13 ...

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... DDR and DDR2 SDRAM High-Performance Controller User Guide Program Device and Implement the Design II logic analyzer to your design, refer to ® Driver. 2–8) or program your targeted Altera Chapter 2: Getting Started AN 380: Test DDR or © March 2009 Altera Corporation ...

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... Native or Avalon Memory-Mapped Controller/Phy Interface AFI or non-AFI Protocol Multiple Controller Clock On or off Sharing © March 2009 Altera Corporation 3. Parameter Settings (ALTMEMPHY). External Memory PHY Interface (ALTMEMPHY). Description Turn on to add the optional error correction coding (ECC) to the design, refer to “Error Correction Coding (ECC)” on page ...

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... DDR and DDR2 SDRAM High-Performance Controller User Guide Chapter 3: Parameter Settings Controller Settings © March 2009 Altera Corporation ...

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... The controller does not do any access reordering. f For more information on the ALTMEMPHY megafunction, refer to the Memory PHY Interface Megafunction User Guide © March 2009 Altera Corporation 4. Functional Description External (ALTMEMPHY). DDR and DDR2 SDRAM High-Performance Controller User Guide ...

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... State Machine Main State Machine Bank Write Data Management Tracking Logic Logic Chapter 4: Functional Description Block Description mem_a mem_ba mem_cas_n mem_cke mem_cs_n mem_dq mem_dqs mem_dm mem_odt ( 1 ) mem_ras_n mem_we_n Address and Command Decode ALTMEMPHY Interface PHY Interface Logic © March 2009 Altera Corporation ...

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... March 2009 Altera Corporation Figure 4–2 on page 4–2 are described in the following sections. DDR and DDR2 SDRAM High-Performance Controller User Guide 4– ...

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... DDR and DDR2 SDRAM High-Performance Controller User Guide ODT enabled: mem_cs[0]or cs[1] mem_cs[2] or cs[3] mem_cs[4] or cs[5] mem_cs[6] or cs[7] Chapter 4: Functional Description Block Description mem_odt[2] mem_odt[0] mem_odt[6] mem_odt[4] © March 2009 Altera Corporation ...

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... We define the read and write latencies as follows. Read latency is the time it takes for the read data to appear at the local interface ■ after you assert the read request signal to the controller. © March 2009 Altera Corporation Table 4–1 Acronym ras_n ...

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... For the half rate controller, the local side frequency is half the memory interface frequency; for the full rate controller equal to the memory interface frequency. Altera defines the read and write latencies in terms of the local interface clock frequency and by the absolute time for the memory controllers. ...

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... Accepts partial writes Creates forced errors to check the functioning of the ECC ■ Powers sensible state ■ © March 2009 Altera Corporation External Memory PHY Interface for more detailed information. DDR and DDR2 SDRAM High-Performance Controller User Guide 4–7 ...

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... Message Codeword Bits Bits From Local Encoder Interface Read Read Codeword Message Bits Bits To Local Decoder- Interface Corrector 32 Bits To and From ECC Local Interface Controller Chapter 4: Functional Description Block Description Bits DDR or DDR2 Memory SDRAM Controller © March 2009 Altera Corporation ...

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... Every bit of this signal vector represents a byte on the data-bus. Thus any of these bits is a signal for the controller not to write to that particular location—a partial write. © March 2009 Altera Corporation Appendix A, ECC Register DDR and DDR2 SDRAM High-Performance Controller User Guide ...

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... A partial write results in a read followed by write in the ECC controller, so latency depends on the time the controller takes to fetch the data from the particular address. DDR and DDR2 SDRAM High-Performance Controller User Guide Chapter 4: Functional Description Block Description © March 2009 Altera Corporation ...

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... Figure 4–4 shows the testbench and the example design. Figure 4–4. Testbench and Example Design Testbench Example Design pnf Example test_complete Driver clock_source © March 2009 Altera Corporation Rate 1 Half 2 Full DDR SDRAM High-Performance Controller ALTMEMPHY Megafunction ...

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... There are two Altera-generated memory models available—associative-array memory model and full-array memory model. The associative-array memory model (<variation name>_mem model.v) allocates reduced set of memory addresses with a default depth of 2,048 or 2K address spaces. ...

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... Table 4–5. Test Status[] Bit Mapping Bit © March 2009 Altera Corporation Test Sequential address test Incomplete write test Data mask pin test Address pin test Power-down test Self-refresh test Auto precharge test DDR and DDR2 SDRAM High-Performance Controller User Guide ...

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... DDR and DDR2 SDRAM High-Performance Controller User Guide shows write accesses with a controller in full-rate mode and Chapter 4: Functional Description Interfaces and Signals © March 2009 Altera Corporation ...

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... PHY - Memory Interface mem_clk mem_addr mem_ba mem_cs_n Mem Command (1) mem_dm mem_dq mem_dqs Note to Figure 4–5: (1) DDR Command and Mem Command show the command that the command signals are issuing. © March 2009 Altera Corporation [2] [3] [ NOP WR NOP ...

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... External Memory PHY Interface Megafunction for more details of this interface. Chapter 4: Functional Description Interfaces and Signals Figure 4–5 on <BBCCDDEE> <1010> <6677> <DDEE> <BBCC> <1 0> <0 1> <0 1> © March 2009 Altera Corporation ...

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... Bursts of size 1 on the local interface are only half as efficient because each request still corresponds to a memory burst of size 4 but only half of the data is used. © March 2009 Altera Corporation shows write accesses with a controller in full-rate mode and DDR and DDR2 SDRAM High-Performance Controller User Guide ...

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... DDR Command and Mem Command show the command that the command signals are issuing. DDR and DDR2 SDRAM High-Performance Controller User Guide [4] [5] [6] [7] [8] [9] 000 PCH ACT PCH Chapter 4: Functional Description Interfaces and Signals [10] [11] [12] [13 ACT © March 2009 Altera Corporation ...

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... ALTMEMPHY megafunction. 8. The controller asserts the control_dqs_burst signals to control the timing of the DQS signal that the ALTMEMPHY megafunction issues to the memory. © March 2009 Altera Corporation Figure 4–6 on <AA> <BB> to local_address = 0x000004 DDR and DDR2 SDRAM High-Performance Controller User Guide ...

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... DDR and DDR2 SDRAM High-Performance Controller User Guide External Memory PHY Interface Megafunction User Guide for more details of this interface. shows write accesses with a controller in half-rate mode and Chapter 4: Functional Description Interfaces and Signals © March 2009 Altera Corporation ...

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... PHY Memory Interface mem_clk mem_addr mem_ba mem_cs_n Mem Command (1) mem_dq mem_dqs[0] Note to Figure 4–7: (1) DDR Command and Mem Command show the command that the command signals are issuing. © March 2009 Altera Corporation [2] [3] 000C 0010 0000 FFFF 0000 0004 0008 000C 0010 ...

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... DDR and DDR2 SDRAM High-Performance Controller User Guide Avalon Interface Specifications for more details. External Memory PHY Interface Megafunction for more details of this interface. shows write accesses with a controller in half-rate mode and Chapter 4: Functional Description Interfaces and Signals Figure 4–7 on © March 2009 Altera Corporation ...

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... PHY Memory Interface mem_clk mem_addr mem_ba mem_cs_n (1) Mem Command mem_dm mem_dqs mem_dq Note to Figure 4–8: (1) DDR Command and Mem Command show the command that the command signals are issuing. © March 2009 Altera Corporation [4] 02 DDCC FFEE NOP WR BBAA FF NOP DDR and DDR2 SDRAM High-Performance Controller User Guide 4– ...

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... External Memory PHY Interface Megafunction for more details of this interface. Chapter 4: Functional Description Interfaces and Signals Figure 4–8 on <BBCCDDEE> <1010> <EE> <DD> <CC> <BB> <1> <0> <1> <1> © March 2009 Altera Corporation ...

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... If the local_ready signal was not asserted, the user logic must keep the read request, size, and address signals asserted. The burst begin signal does not need to be held asserted if the ready signal is not asserted. f Refer to © March 2009 Altera Corporation [4] [5] [ ...

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... DDR and DDR2 SDRAM High-Performance Controller User Guide Chapter 4: Functional Description Interfaces and Signals External Memory PHY Interface Megafunction for more details of this interface. © March 2009 Altera Corporation ...

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... The user logic requests a second read to a different address, again of size the memory side). The controller is able to buffer up to four requests so the local_ready signal stays high and the request is accepted. © March 2009 Altera Corporation shows three consecutive read requests of the same burst [4] [5] ...

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... DDR and DDR2 SDRAM High-Performance Controller User Guide External Memory PHY Interface Megafunction for more details of this interface. shows three consecutive read requests of the same burst Chapter 4: Functional Description Interfaces and Signals © March 2009 Altera Corporation ...

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... PHY Memory Interface mem_clk mem_addr mem_ba mem_cs_n Mem Command (1) 0 mem_dq mem_dqs[0] Note to Figure 4–11: (1) DDR Command and Mem Command show the command that the command signals are issuing. © March 2009 Altera Corporation [3] [4] [5] [9] [11] 80A PCH ...

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... DDR and DDR2 SDRAM High-Performance Controller User Guide Chapter 4: Functional Description External Memory PHY Interface Megafunction User Guide for more details of this interface. Interfaces and Signals Figure 4–11. © March 2009 Altera Corporation ...

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... Full Rate, Native Interface Mode—Alternate Read-Write Figure 4–12 on page 4–32 and using the Local Interface Protocol setting set to Native interface. © March 2009 Altera Corporation shows read, write, read, write operation in full-rate mode DDR and DDR2 SDRAM High-Performance Controller User Guide ...

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... NOP RD NOP WR NOP AABB 0FF 4 0000 8 0000 10 WR NOP RD NOP WR [4] [5] [12] [16] [17] [24] Chapter 4: Functional Description Interfaces and Signals [22] [6] [23] [19] 1 FFFF CCDD FFFF 3 0000 0 NOP [18] © March 2009 Altera Corporation ...

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... ALTMEMPHY megafunction for it to send to the memory device. 15. The controller asserts the control_doing_rd signal to indicate to the ALTMEMPHY megafunction how many clock cycles of read data it should expect. © March 2009 Altera Corporation External Memory PHY Interface Megafunction User for more details of this interface. ...

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... DDR Command shows the command that the command signals are issuing. DDR and DDR2 SDRAM High-Performance Controller User Guide [2] [ 0400 0400 0000 0 PCH NOP ARF NOP Chapter 4: Functional Description Interfaces and Signals [ ARF ARF NOP © March 2009 Altera Corporation ...

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... You must not assert both request signals at the same time. Undefined behavior occurs if both local_powerdn_req and local_self_rfsh_req are asserted simultaneously. © March 2009 Altera Corporation Figure 4–14 and Figure 4–15 on ...

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... DDR and DDR2 SDRAM High-Performance Controller User Guide (1) (2) (3) (1) (2) Specifications). You can assert it anytime, but once you have Chapter 4: Functional Description Interfaces and Signals (4) (5) (3) (4) © March 2009 Altera Corporation ...

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... March 2009 Altera Corporation Direction Input The asynchronous reset input to the controller. All other reset signals are derived from resynchronized versions of this signal. This signal holds the complete ALTMEMPHY megafunction, including the PLL, in reset while low. ...

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... Should be connected to the ALT_OCT megafunction output parallelterminationcontrol. Input Allows the use of DLL in another ALTMEMPHY instance in this ALTMEMPHY instance. Connect the export port on the ALTMEMPHY instance with a DLL to the import port on the other ALTMEMPHY instance. Chapter 4: Functional Description Interfaces and Signals Description © March 2009 Altera Corporation ...

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... Table 4–7. Local Interface Signals (Part Signal Name Direction Input local_address[] © March 2009 Altera Corporation shows the DDR and DDR2 SDRAM high-performance Description Memory address at which the burst should start. ■ Full rate controllers The width of this bus is sized using the following equation: For one chip select: width = bank bits + row bits + column bits – ...

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... Write data bus. The width of local_wdata is twice that of the memory data bus for a full rate controller; four times the memory data bus for a half rate controller. Chapter 4: Functional Description Interfaces and Signals 0110 >< 1010 > © March 2009 Altera Corporation ...

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... Output local_wdata_req Input local_autopch_req © March 2009 Altera Corporation Description Write request signal. You cannot assert read request and write request signal at the same time. When the memory initialization, training, and calibration are complete, the ALTMEMPHY sequencer asserts the ctrl_usr_mode_rdy signal to the memory controller, which then asserts this signal to indicate that the memory interface is ready to be used ...

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... Memory data bus. This bus is half the width of the local read and write data busses. Memory data strobe signal, which writes data into the DDR or DDR2 SDRAM and captures read data into the Altera device. Clock for the memory device. Inverted clock for the memory device. ...

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... ECC controller signals. Table 4–9. ECC Controller Signals Signal Name ecc_addr[] ecc_be[] ecc_interrupt ecc_rdata[] ecc_read_req ecc_wdata[] ecc_write_req © March 2009 Altera Corporation Description Memory write enable signal. Direction Input Address for ECC controller. Input ECC controller byte enable. Output Interrupt from ECC controller. ...

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... DDR and DDR2 SDRAM High-Performance Controller User Guide Chapter 4: Functional Description Interfaces and Signals © March 2009 Altera Corporation ...

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... Cyclone III device, and half-rate implementation on a Windows-based system. The principles in this design example are the same for any other mode of the Altera DDR and DDR2 SDRAM high- performance ALTMEMPHY-based memory controllers. Creating A Simulation Testbench Environment The Megawizard Plug-In Manager automatically generates an example testbench ...

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... It can also be used to check if your memory interface is working in hardware. DDR and DDR2 SDRAM High-Performance Controller User Guide Chapter 5: Example Design Walkthrough Understanding the Example Design and Testbench for further information on PLL. External for further © March 2009 Altera Corporation ...

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... On the File menu, click Change Directory. 3. Select <your project name>/simulation/modelsim and click OK the Tools menu, click Execute Macro. 5. Select <your project name>_run_msim_rtl_verilog.do and click OK. © March 2009 Altera Corporation AN 380: Test DDR or DDR2 SDRAM Interfaces on Driver. AN 328: Interfacing DDR2 SDRAM with Stratix II, Stratix II Devices ...

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... ModelSim-AE includes all Altera device libraries .do script for ModelSim-AE does not compile these libraries. NativeLink includes the relevant libraries for other simulators. f Refer to Altera-supported RTL simulation tools. The Testbench Stages Before the user logic (example driver) can read or write to the local interface, the external SDRAM must first be initialized and calibrated ...

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... Figure 5–2, the expected waveform view of the initialization phase is directly following the NOP of 200 µs. Steps is complete by the second yellow cursor. Additional signals are added to simplify debugging. © March 2009 Altera Corporation are expanded to increase detail. Initialization DDR and DDR2 SDRAM High-Performance Controller User Guide ...

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Figure 5–2. Simulation Initialization Phase ...

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... The example testbench stops when either test_complete is asserted or when 200,000 mem_clk cycles after the t © March 2009 Altera Corporation (Native interface only) (Avalon-MM interface only) External Memory PHY Interface (ALTMEMPHY). ...

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... The data on the read data bus should match that on the write data bus during the read process. DDR and DDR2 SDRAM High-Performance Controller User Guide Chapter 5: Example Design Walkthrough shows the series of writes followed by reads on both the local The Testbench Stages © March 2009 Altera Corporation ...

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Figure 5–3. Functional Memory Use Stage ...

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... DDR and DDR2 SDRAM High-Performance Controller User Guide Chapter 5: Example Design Walkthrough The Testbench Stages © March 2009 Altera Corporation ...

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... Current single-bit error 03 count Current double-bit error 04 count Last or first single-bit error 05 error address Last or first double-bit error 06 error address © March 2009 Altera Corporation A. ECC Register Description Size (Bits) Attribute Default 32 R/W 0000000F This register contains all commands for the ECC functioning. 32 ...

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... Table cleared by writing the respective locations. ECC Registers Description Table A–3). Table A–4). A–5). These status bits can be A–6). These status bits can be © March 2009 Altera Corporation ...

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... Table A–3. Interrupt Status Register Bit Others Table A–4 shows the interrupt mask register. © March 2009 Altera Corporation Direction Decoder-corrector When 1, count single-bit errors. Decoder-corrector When 1, correct single-bit errors. Decoder-corrector When 1, detect all double-bit errors and increment double-bit error counter. N/A Reserved for future use ...

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... Interrupt When 0, no single-bit error; when 1, single-bit error occurred in this 64-bit part. Reserved Reserved. Name Cause of Interrupt When 0, no double-bit error; when 1, double- bit error occurred in this 64-bit part. Reserved Reserved. Register Bits Description Description Description © March 2009 Altera Corporation ...

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... Added Cyclone III support. December 2006 6.1 First release. How to Contact Altera For the most up-to-date information about Altera products, see the following table. Contact Technical support Technical training Altera literature services Non-technical support (General) © March 2009 Altera Corporation ...

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... Info–2 Contact (Software Licensing) Note: (1) You can also contact your local Altera sales office or sales representative. Typographic Conventions The following table shows the typographic conventions that this document uses. Visual Cue Bold Type with Initial Capital Letters bold type Italic Type with Initial Capital Letters ...