IPR-SDRAM/HPDDR2 Altera, IPR-SDRAM/HPDDR2 Datasheet - Page 65

• Manufacturer Part Number: IPR-SDRAM/HPDDR2
• Description: IP CORE Renewal Of IP-SDRAM/HDDR2
• Manufacturer: Altera

Specifications of IPR-SDRAM/HPDDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Stratix FPGAs, Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 4: Functional Description
Interfaces and Signals
Signals
Table 4–6. Clock and Reset Signals (Part 1 of 2)
© March 2009 Altera Corporation
global_reset_n
pll_ref_clk
phy_clk
reset_phy_clk_n
aux_full_rate_clk
aux_half_rate_clk
dll_reference_clk
reset_request_n
soft_reset_n
oct_ctl_rs_value
Name
1
If your MegaCore variation is configured to support local burst sizes greater than one,
note that local_autopch is ignored unless you request a complete burst. It is not
possible to auto-precharge a partial burst to the memory.
Table 4–6
shows the clock and reset signals.
Direction
Output
Output
Output
Output
Output
Output
Input
Input
Input
Input
The asynchronous reset input to the controller. All other reset signals
are derived from resynchronized versions of this signal. This signal
holds the complete ALTMEMPHY megafunction, including the PLL, in
reset while low.
The reference clock input to PLL.
The system clock that the ALTMEMPHY megafunction provides to the
user. All user inputs to and outputs from the DDR high-performance
controller must be synchronous to this clock.
The reset signal that the ALTMEMPHY megafunction provides to the
user. It is asserted asynchronously and deasserted synchronously to
phy_clk clock domain.
An alternative clock that the ALTMEMPHY megafunction provides to
the user. This clock always runs at the same frequency as the external
memory interface. In half-rate mode, this clock is twice the frequency
of the phy_clk and can be used whenever a 2x clock is required. In
full-rate mode, this clock is driven by the same PLL output as the
phy_clk signal.
An alternative clock that the ALTMEMPHY megafunction provides to
the user. This clock always runs at half the frequency as the external
memory interface. In full-rate mode, this clock is half the frequency of
the phy_clk and can be used, for example to clock the user side of a
half-rate bridge. In half-rate mode, this clock is driven by the same
PLL output as the phy_clk signal.
Reference clock to feed to an externally instantiated DLL.
Reset request output that indicates when the PLL outputs are not
locked. Use this signal as a reset request input to any system-level
reset controller you may have. This signal is always low while the PLL
is locking, and so any reset logic using it is advised to detect a reset
request on a falling edge rather than by level detection.
Edge detect reset input intended for SOPC Builder use or to be
controlled by other system reset logic. It is asserted to cause a
complete reset to the PHY, but not to the PLL used in the PHY.
ALTMEMPHY signal that specifies the serial termination value. Should
be connected to the ALT_OCT megafunction output
seriesterminationcontrol.
DDR and DDR2 SDRAM High-Performance Controller User Guide
Description
4–37