IPR-SDRAM/HPDDR2 Altera, IPR-SDRAM/HPDDR2 Datasheet - Page 25

• Manufacturer Part Number: IPR-SDRAM/HPDDR2
• Description: IP CORE Renewal Of IP-SDRAM/HDDR2
• Manufacturer: Altera

Specifications of IPR-SDRAM/HPDDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Stratix FPGAs, Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 2: Getting Started
Compile the Design
Compile the Design
© March 2009 Altera Corporation
To use the Quartus II software to compile the example design and perform post-
compilation timing analysis, follow these steps:
1. Set up the TimeQuest timing analyzer:
2. Use one of the following procedures to specify I/O standard assignments for pins:
■
■
3. Set the top-level entity to the top-level design.
a. On the Assignments menu, click Timing Analysis Settings, select Use
b. Add the Synopsys Design Constraints (.sdc) file,
c. Add the .sdc file for the example top-level design,
If you have a single DDR or DDR2 SDRAM interface, and your top-level pins have
default naming shown in the example design, run
<variation name>_pin_assignments.tcl.
If your design contains pin names that do not match the design, edit the
<variation name>_pin_assignments.tcl file before you run the script. Follow these
steps:
a. Open <variation name>_pin_assignments.tcl file.
b. Based on the flow you are using, set the sopc_mode value to Yes or No.
c. Type your preferred prefix in the pin_prefix variable. For example, to add
a. On the File menu, click Open.
b. Browse to your SOPC Builder system top-level design or <variation
c. On the Project menu, click Set as Top-Level Entity.
TimeQuest Timing Analyzer during compilation, and click OK.
<variation name>_phy_ddr_timing.sdc, to your project. On the Project menu,
click Add/Remove Files in Project and browse to select the file.
<variation name>_example_top.sdc, to your project. This file is only required if
you are using the example as the top-level design.
■
if {![info exists sopc_mode]} {set sopc_mode YES}
■
if {![info exists sopc_mode]} {set sopc_mode NO}
the prefix my_mem, do the following:
if {![info exists set_prefix}{set pin_prefix “my_mem_”}
After setting the prefix, the pin names are expanded as shown in the following:
■
my_mem_cs_n_from_the_
■
my_mem_cs_n[0]
name>_example_top if you are using MegaWizard Plug-In Manager, and click
Open.
SOPC Builder System flow:
MegaWizard Plug-In Manager flow:
SOPC Builder System flow:
MegaWizard Plug-In Manager flow:
<your instance name>
DDR and DDR2 SDRAM High-Performance Controller User Guide
2–13