IPR-SDRAM/HPDDR2 Altera, IPR-SDRAM/HPDDR2 Datasheet - Page 26

• Manufacturer Part Number: IPR-SDRAM/HPDDR2
• Description: IP CORE Renewal Of IP-SDRAM/HDDR2
• Manufacturer: Altera

Specifications of IPR-SDRAM/HPDDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Stratix FPGAs, Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

2–14
Program Device and Implement the Design
DDR and DDR2 SDRAM High-Performance Controller User Guide
f
4. Assign the DQ and DQS pin locations.
5. For Stratix III and Stratix IV designs, if you are using advanced I/O timing, specify
6. Select your required I/O driver strength (derived from your board simulation) to
7. To compile the design, on the Processing menu, click Start Compilation.
To attach the SignalTap
DDR2 SDRAM Interfaces on Hardware Using the Example
After you have compiled the example design, you can perform RTL simulation (refer
to
device to verify the example design in hardware.
To implement your design based on the example design, replace the example driver
in the example design with your own logic.
“Simulate the Example Design” on page
a. You should assign pin locations to the pins in your design, so the Quartus II
b. Use either the Pin Planner or Assignment Editor to assign the clock source pin
1
board trace models in the Device & Pin Options dialog box. If you are using any
other device and not using advanced I/O timing, specify the output pin loading
for all memory interface pins.
ensure that you correctly drive each signal or ODT setting and do not suffer from
overshoot or undershoot.
software can perform fitting and timing analysis correctly.
manually. Also choose which DQS pin groups should be used by assigning
each DQS pin to the required pin. The Quartus II Fitter then automatically
places the respective DQ signals onto suitable DQ pins within each group.
When assigning pins in your design, ensure that you set an appropriate I/O
standard for the non-memory interfaces, such as the clock source and the
reset inputs. For example, for DDR SDRAM select 2.5 V and for DDR2
SDRAM select 1.8 V. Also select in which bank or side of the device you
want the Quartus II software to place them.
®
II logic analyzer to your design, refer to
2–8) or program your targeted Altera
Program Device and Implement the Design
Driver.
© March 2009 Altera Corporation
AN 380: Test DDR or
Chapter 2: Getting Started