IPR-SDRAM/HPDDR2 Altera, IPR-SDRAM/HPDDR2 Datasheet - Page 62

• Manufacturer Part Number: IPR-SDRAM/HPDDR2
• Description: IP CORE Renewal Of IP-SDRAM/HDDR2
• Manufacturer: Altera

Specifications of IPR-SDRAM/HPDDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Stratix FPGAs, Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

4–34
Figure 4–13. User Refresh Control
Note to
(1) DDR Command shows the command that the command signals are issuing.
DDR and DDR2 SDRAM High-Performance Controller User Guide
Figure
DDR Command (1)
local_refresh_ack
4–13:
local_refresh_req
Controller Interface
Local Interface
ddr_cas_n
ddr_ras_n
ddr_we_n
ddr_cs_n
ddr_cke
reset_n
ddr_ba
ddr_a
clk
16. The ALTMEMPHY megafunction issues the second read command to the memory
17. The memory returns the second read data to the ALTMEMPHY megafunction.
18. The ALTMEMPHY megafunction returns data to the controller by asserting the
19. The controller returns the second read data to user by asserting the
20. The user logic requests the second write by asserting the write request signal. In
21. In native interface mode, the controller requests write data and byte enables from
22. The controller issues the second memory write command and address signals to
23. The controller asserts the control_wdata_valid signal to indicate to the
24. The ALTMEMPHY megafunction issues the second write command and sends the
User Refresh Control
Figure 4–13
when the controller issues refreshes to the memory. This feature allows better control
of worst case latency and allows refreshes to be issued in bursts to take advantage of
idle periods.
and captures the read data from the memory.
control_rdata_valid signal.
local_rdata_valid signal when there is a valid read data on the
local_rdata bus.
this example, the request is a burst length of 2.
the user logic by asserting local_wdata_req. The local_wdata (0xCCDD) and
local_be signals must be presented one clock cycle after local_wdata_req is
asserted.
the ALTMEMPHY megafunction for it to send to the memory device.
ALTMEMPHY megafunction that valid write data and write data masks are
present on the inputs to the ALTMEMPHY megafunction.
second write data and write DQS to the memory.
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shows the user refresh control interface. This feature allows you to control
[1]
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[2]
[3]
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0
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ARF
ARF
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[4]
Chapter 4: Functional Description
© March 2009 Altera Corporation
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Interfaces and Signals