IPR-SDRAM/HPDDR2 Altera, IPR-SDRAM/HPDDR2 Datasheet - Page 83

• Manufacturer Part Number: IPR-SDRAM/HPDDR2
• Description: IP CORE Renewal Of IP-SDRAM/HDDR2
• Manufacturer: Altera

Specifications of IPR-SDRAM/HPDDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Stratix FPGAs, Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

ECC Registers
Table A–1. ECC Registers (Part 1 of 2)
© March 2009 Altera Corporation
Control word specifications
Maximum single-bit error
counter threshold
Maximum double-bit error
counter threshold
Current single-bit error
count
Current double-bit error
count
Last or first single-bit error
error address
Last or first double-bit error
error address
Name
This appendix describes the ECC registers and the register bits.
Table A–1
Address
00
01
02
03
04
05
06
shows the ECC registers.
(Bits)
Size
32
32
32
32
32
32
32
Attribute
R/W
R/W
R/W
RO
RO
RO
RO
00000001
00000001
00000000
00000000
00000000
00000000
0000000F
Default
DDR and DDR2 SDRAM High-Performance Controller User Guide
A. ECC Register Description
This register contains all commands for
the ECC functioning.
The single-bit error counter increments
(when a single-bit error occurs) until the
maximum threshold, as defined by this
register. When this threshold is crossed,
the ECC generates an interrupt.
The double-bit error counter increments
(when a double-bit error occurs) until the
maximum threshold, as defined by this
register. When this threshold is crossed,
the ECC generates an interrupt.
The single-bit error counter increments
(when a single-bit error occurs) until the
maximum threshold. You can find the
value of the count by reading this status
register.
The double-bit error counter increments
(when a double-bit error occurs) until the
maximum threshold. You can find the
value of the count by reading this status
register.
This status register stores the last single-
bit error error address. It can be cleared
using the control word clear. If bit 10 of
the control word is set high, the first
occurred address is stored.
This status register stores the last
double-bit error error address. It can be
cleared using the control word clear. If bit
10 of the control word is set high, the
first occurred address is stored.
Description