IPR-SDRAM/HPDDR2 Altera, IPR-SDRAM/HPDDR2 Datasheet - Page 63

• Manufacturer Part Number: IPR-SDRAM/HPDDR2
• Description: IP CORE Renewal Of IP-SDRAM/HDDR2
• Manufacturer: Altera

Specifications of IPR-SDRAM/HPDDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Stratix FPGAs, Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 4: Functional Description
Interfaces and Signals
© March 2009 Altera Corporation
The following sequence corresponds with the numbered items in
1. The user logic asserts the refresh request signal to indicate to the controller that it
2. The controller asserts the refresh acknowledge signal to indicate that it has sent a
3. The user logic keeps the refresh request signal asserted to indicate that it wishes to
The controller again asserts the refresh acknowledge signal to indicate that it has
issued a refresh. At this point the user logic deasserts the refresh request signal and
the controller continues with the reads and writes in its buffers.
Self-Refresh and Power-Down Commands
This feature allows you to direct the controller to put the external memory device into
a low-power state. There are two possible low-power states: self-refresh and power
down. The controller supports both and manages the necessary memory timings to
ensure that the data in the memory is maintained at all times.
The local interface input pins (local_powerdn_req, and local_self_rfsh_req)
allow you to direct the controller to place the memory device in power-down or self-
refresh mode, respectively. The local interface output pins (local_powerdn_ack,
and local_self_rfsh_ack) allow the controller to acknowledge the request and
also indicate the current state of the memory.
If either local_powerdn_ack or local_self_rfsh_ack signal is asserted, the
memory is in the relevant low-power mode. Both pairs of signals follow the same
basic protocol as shown in
pair of signals follows the same timing and behavior as the power-down pair. The
only difference is that the local_refresh_ack signal is not asserted in self-refresh
mode as the controller does not refresh the memory when the memory is in self-
refresh mode.
You must not assert both request signals at the same time. Undefined behavior occurs
if both local_powerdn_req and local_self_rfsh_req are asserted
simultaneously.
should perform a refresh. The read and write requests signal do not need to be
interrupted or paused in any way. If the user logic asserts refresh_req, the
controller stops taking commands from its internal queue and services the refresh
first (although the controller may have to wait a few cycles until it is legal to do the
precharge-all command that comes before the refresh).
1
refresh command to the ALTMEMPHY megafunction. The exact time that the
refresh command occurs on the memory interface depends on the ALTMEMPHY
megafunction command output latency. This signal is still available even if the
Enable user auto-refresh controls option is not turned on, allowing the user logic
to track when the controller issues refreshes.
perform another refresh request.
Refresh requests are higher priority requests that go straight past the
command queue. If the read and write queue is not yet full, the controller
accepts more commands and holds them until it starts to read or write
again. As soon as the refresh operation is completed, the controller
continues processing the commands in the queue.
Figure 4–14
and
DDR and DDR2 SDRAM High-Performance Controller User Guide
Figure 4–15
on
page
4–36. The self-refresh
Figure
4–13.
4–35