IPR-SDRAM/HPDDR2 Altera, IPR-SDRAM/HPDDR2 Datasheet - Page 21

• Manufacturer Part Number: IPR-SDRAM/HPDDR2
• Description: IP CORE Renewal Of IP-SDRAM/HDDR2
• Manufacturer: Altera

Specifications of IPR-SDRAM/HPDDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Stratix FPGAs, Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 2: Getting Started
MegaWizard Plug-In Manager Flow
© March 2009 Altera Corporation
f
4. On the New Test Bench Settings dialog box, do the following:
5. On the Processing menu, point to Start and click Start Analysis & Elaboration to
6. On the Tools menu, point to Run EDA Simulation Tool and click EDA RTL
If your Quartus II project appears to be configured correctly but the example
testbench still fails, check the known issues on the
filing a service request.
For a complete MegaWizard Plug-In Manager system design example containing the
DDR and DDR2 SDRAM high-performance controller MegaCore function, refer to
Chapter 5, Example Design
IP Functional Simulations
For VHDL simulations with IP functional simulation models, perform the following
steps:
1. Create a directory in the <project directory>\testbench directory.
a. Type a name for the Test bench name.
b. In Top level module in test bench, type the name of the automatically
c. In Design instance in test bench, type the name of the top-level instance, dut.
d. Under Simulation period, set End simulation at to 600 µs.
e. Add the testbench files and automatically-generated memory model files. In
f
f. Select the files and click OK.
start analysis.
Simulation.
1
generated testbench, <variation name>_example_top_tb.
the File name field, browse to the location of the memory model and the
testbench, click Open and then click Add. The testbench is
<variation name>_example_top_tb.v; memory model is
<variation name>_mem_model.v.
Ensure that the Quartus II EDA Tool Options are configured correctly for
your simulation environment. On the Tools menu, click Options. In the
Category list, click EDA Tool Options and verify the locations of the
executable files.
The auto generated generic SDRAM model may be used as a placeholder
for a specific memory vendor supplied model. For information on how to
replace the generic model with a vendor specific model, refer to “Perform
RTL/Functional Simulation (Optional)” in
SDRAM with Stratix II, Stratix II GX, and Arria GX
Walkthrough.
DDR and DDR2 SDRAM High-Performance Controller User Guide
Knowledge Database
AN 328: Interfacing DDR2
Devices.
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