IPR-SDRAM/HPDDR2 Altera, IPR-SDRAM/HPDDR2 Datasheet - Page 54

• Manufacturer Part Number: IPR-SDRAM/HPDDR2
• Description: IP CORE Renewal Of IP-SDRAM/HDDR2
• Manufacturer: Altera

Specifications of IPR-SDRAM/HPDDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Stratix FPGAs, Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

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DDR and DDR2 SDRAM High-Performance Controller User Guide
2. The user logic requests a second read to a different address, again of size 2 (4 on
3. The user logic requests a third read to a different address, of size 2 (4 on the
4. The controller issues the necessary memory command and address signals to the
5. The controller asserts the control_doing_rd signal to indicate to the
6. The ALTMEMPHY megafunction issues the read commands to the memory and
7. The ALTMEMPHY megafunction returns data to the controller after
8. The controller returns the read data to the user by asserting the
the memory side). The controller is able to buffer up to four requests so the
local_ready signal stays high and the request is accepted.
memory side). The local_ready signal remains asserted, which indicates that
the controller has accepted the request.
ALTMEMPHY megafunction for it to send to the memory device.
ALTMEMPHY megafunction how many clock cycles of read data it should expect.
The ALTMEMPHY megafunction uses the control_doing_rd signal to enable
its capture registers for the expected duration of the memory burst.
f
captures the read data from the memory.
resynchronizing it to the phy_clk domain by asserting the
control_rdata_valid signal when there is valid read data on the
control_rdata bus.
local_rdata_valid signal when there is valid read data on the local_rdata
bus. If Enable error correction and detection logic is disabled, there is no delay
between the control_rdata and the local_rdata buses. If there is ECC logic
in the controller, there is one or three clock cycles of delay between the
control_rdata and local_rdata buses.
Refer to the “Handshake Mechanism Between Read Commands and
Read Data” section of the
User Guide (ALTMEMPHY)
External Memory PHY Interface Megafunction
for more details of this interface.
Chapter 4: Functional Description
© March 2009 Altera Corporation
Interfaces and Signals