IPR-SRAM/QDRII Altera, IPR-SRAM/QDRII Datasheet - Page 26

• Manufacturer Part Number: IPR-SRAM/QDRII
• Description: IP CORE Renewal Of IP-SRAM/QDRII
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SRAM/QDRII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: HardCopy II, Stratix
• Features: Automatic Concatenation Of Consecutive Reads And Writes, Easy-to-Use IP Toolbench Interface
• Core Architecture: FPGA
• Core Sub-architecture: HardCopy, Stratix
• Rohs Compliant: NA
• Function: QDRII SRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Simulate the Example Design
2–16
QDRII SRAM Controller MegaCore Function User Guide
auk_qdrii_lib
Table 2–4. Files to Compile—Verilog HDL IP Functional Simulation Models (Part 2 of 2)
Library
4.
5.
Verilog HDL Gate-Level Simulations
For Verilog HDL simulations with gate-level models, follow these steps:
<project directory>/<variation name>_auk_qdrii_sram_clk_gen.v
<project directory>/<variation name>_auk_qdrii_sram_addr_cmd_reg.v
<project directory>/<variation name>_auk_qdrii_sram_cq_cqn_group.v
<project directory>/<variation name>_auk_qdrii_sram_read_group.v
<project directory>/<variation
name>_auk_qdrii_sram_capture_group_wrapper.v
<project directory>/<variation name>_auk_qdrii_sram_resynch_reg.v
<project directory>/<variation name>_auk_qdrii_sram_write_group.v
<project directory>/<variation name>_auk_qdrii_sram_datapath.v
<project directory>/<variation name>_auk_qdrii_sram_test_group.v
<project directory>/<variation name>_auk_qdrii_sram_train_wrapper.v
<project directory>/<variation name>_auk_qdrii_sram_pipeline_wdata.v
<project directory>/<variation name>_auk_qdrii_sram_pipeline_rdata.v
<project directory>/<variation
name>_auk_qdrii_sram_pipeline_addr_cmd.v
<project directory>/<variation
name>_auk_qdrii_sram_pipe_resynch_wrapper.v
<project directory>/<variation
name>_auk_qdrii_sram_avalon_controller_ipfs_wrap.vo
<project directory>/<variation name>_auk_qdrii_sram.v
<project directory>/<variation name>.v
<project directory>/qdrii_pll_stratixii.v
<project directory>/<variation name>_auk_qdrii_sram_dll.v
<project directory>/<variation name>_auk_qdrii_sram_example_driver.v
<project directory>/<project name>.v
<project directory>/testbench/<project name>_tb.vhd
Set the Tcl variable gRTL_DELAYS to 1, which tells the testbench to
model the extra delays in the system necessary for RTL simulation.
Configure your simulator to use transport delays, a timestep of
picoseconds and to include the auk_qdrii_lib, sgate_ver, lpm_ver,
altera_mf_ver, and <device name>_ver libraries.
MegaCore Version 9.1
Filename
Altera Corporation
November 2009