IPR-SRAM/QDRII Altera, IPR-SRAM/QDRII Datasheet - Page 36

• Manufacturer Part Number: IPR-SRAM/QDRII
• Description: IP CORE Renewal Of IP-SRAM/QDRII
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SRAM/QDRII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: HardCopy II, Stratix
• Features: Automatic Concatenation Of Consecutive Reads And Writes, Easy-to-Use IP Toolbench Interface
• Core Architecture: FPGA
• Core Sub-architecture: HardCopy, Stratix
• Rohs Compliant: NA
• Function: QDRII SRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Block Description
3–4
QDRII SRAM Controller MegaCore Function User Guide
Write Data Pipeline
The write data pipeline pipelines the write data by a specified number of
clock cycles.The number of pipelines is equal to the address and
command pipelines, because the controller already aligns the data,
address and command correctly, therefore the amount of delay going to
the I/O is identical.
Training Group Module
The training group module sends all the control, data, and address
during training; it reverts to the controller-issued signals after training. It
also pauses the controllers for the duration of the training and sends some
feedback to the resynchronization logic to realign the pointers to get to
the desired latency. To ensure stability the read pointer is aligned only
after the DLL is stable. The write pointer is synchronously reset after the
read pointer. You can view the training signals from outside the example
design.
Read Data Pipeline
The optional read data pipeline pipelines the data after it is
resynchronized by a predefined number of cycles.
Resynchronization Logic
The resynchronization logic transfers the data from the QDRII SRAM
clock domain onto the system clock domain.
A small dual-port RAM block resynchronizes the data onto the system
clock. It writes and reads data every cycle. The frequency is the same on
either side.
The amount of buffering in the dual-port RAM automatically
compensates for any phase effects. However, there is no way of knowing
in which cycle the data is valid. Also the latency may vary from board to
board, even device to device depending on the timing relationship of the
clocks. Thus the training group module guarantees that each QDRII
device has the same read latency and that the latency is fixed and known
at startup.
Data is sent to a specific address. The same address is read at the same
time. It takes a certain amount of time to propagate the first data to the
memory and read it back. This first set of clock cycles is deemed invalid
and is not taken into account.
MegaCore Version 9.1
Altera Corporation
November 2009