IPR-SRAM/QDRII Altera, IPR-SRAM/QDRII Datasheet - Page 46

• Manufacturer Part Number: IPR-SRAM/QDRII
• Description: IP CORE Renewal Of IP-SRAM/QDRII
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SRAM/QDRII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: HardCopy II, Stratix
• Features: Automatic Concatenation Of Consecutive Reads And Writes, Easy-to-Use IP Toolbench Interface
• Core Architecture: FPGA
• Core Sub-architecture: HardCopy, Stratix
• Rohs Compliant: NA
• Function: QDRII SRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Interfaces & Signals
Figure 3–10. Write—Burst of Four (Narrow Mode)
3–14
QDRII SRAM Controller MegaCore Function User Guide
avl_wait_request_wr
avl_data_wr[35:0]
avl_adr_wr[19:0]
qdrii_bwsn[1:0]
avl_clock_wr
qdrii_d[17:0]
qdrii_a[19:0]
system_clk
qdrii_wpsn
avl_write
avl_clk
This section does not illustrate the burst of two example, because you can
transfer any data at any address in every Avalon clock cycle. The timing
of the qdrii_a signal is different, refer to
Bursts with Pauses
There are no pauses when using a burst of two memories. For the burst of
four, there are some pauses (depending on the mode). In narrow mode, if
the transfers are to consecutive addresses all the time, no pause occurs. If
the transfers are to non-consecutive addresses, a pause may occur, refer
to
conditions:
■
■
Figure 3–11 on page
00010002
A one-cycle write to address <a> followed straight away by a two-
cycle transfer to addresses <b> and <b + 1>
The second half of the transfer to <b> is paused for a clock cycle
0002
MegaCore Version 9.1
00030004
00030004
0003
3–15. a pause occurs only in the following
0002
Figure 3–7 on page
0001 0002 0003 0004
00
00
Altera Corporation
November 2009
0004
3–11.