IPR-SRAM/QDRII Altera, IPR-SRAM/QDRII Datasheet - Page 53

• Manufacturer Part Number: IPR-SRAM/QDRII
• Description: IP CORE Renewal Of IP-SRAM/QDRII
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SRAM/QDRII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: HardCopy II, Stratix
• Features: Automatic Concatenation Of Consecutive Reads And Writes, Easy-to-Use IP Toolbench Interface
• Core Architecture: FPGA
• Core Sub-architecture: HardCopy, Stratix
• Rohs Compliant: NA
• Function: QDRII SRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Figure 3–18. Simultaneous Read & Write—Burst of Two
Altera Corporation
November 2009
avl_wait_request_wr
avl_wait_request_rd
avl_data_read_valid
avl_data_wr[17:0]
avl_data_rd[17:0]
avl_adr_wr[19:0]
avl_adr_rd[19:0]
qdrii_a[19:0]
qdrii_d[17:0]
qdrii_q[17:0]
qdrii_wpsn
qdrii_rpsn
qdrii_cqn
avl_read
avl_write
qdrii_cq
avl_clk
qdrii_k
1112
51
01
Burst of Four (Wide Mode)
For the burst of four (wide mode) all the data is present in one clock cycle.
Similarly to the two cycles, you must alternate the read and write
commands on the QDRII SRAM interface. As a result, there is a pause
when both the read and write commands arrive simultaneously on the
Avalon interfaces. The first read is buffered and then the consecutive read
is delayed by one clock cycle, refer to
1314
1314
52
52
02
02
MegaCore Version 9.1
51 01 52 02
11 12 13 14
QDRII SRAM Controller MegaCore Function User Guide
14
02
Figure 3–19 on page
01 02 03 04
04
Functional Description
0102
3–22.
0304
0304
3–21