IPR-SRAM/QDRII Altera, IPR-SRAM/QDRII Datasheet - Page 50

• Manufacturer Part Number: IPR-SRAM/QDRII
• Description: IP CORE Renewal Of IP-SRAM/QDRII
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SRAM/QDRII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: HardCopy II, Stratix
• Features: Automatic Concatenation Of Consecutive Reads And Writes, Easy-to-Use IP Toolbench Interface
• Core Architecture: FPGA
• Core Sub-architecture: HardCopy, Stratix
• Rohs Compliant: NA
• Function: QDRII SRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Interfaces & Signals
Figure 3–15. Burst—Burst of Four (Narrow Mode)
3–18
QDRII SRAM Controller MegaCore Function User Guide
avl_wait_request_rd
avl_data_read_valid
avl_data_rd[19:0]
avl_data_rd[17:0]
qdrii_a[19:0]
qdrii_q[17:0]
qdrii_rpsn
qdrii_cqn
avl_read
qdrii_cq
avl_clk
qdrii_k
0002
Bursts with Pauses
Bursts with pauses only applies to bursts of four, (narrow mode). When
several read requests to non-consecutive addresses occur, it takes more
time to get the data from the memory (it take two cycles per read access)
than time needed to request them.
followed by two reads to consecutive addresses. As the first two requests
are not to consecutive addresses, the controller has to pause the read
requests to insert a clock cycle. The following two reads still get
concatenated to make a burst of four, avoiding loss of bandwidth.
0003
MegaCore Version 9.1
0002
Figure 3–16 on page 3–19
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04
0102
Altera Corporation
November 2009
0304
0304
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