IPR-SRAM/QDRII Altera, IPR-SRAM/QDRII Datasheet - Page 61

• Manufacturer Part Number: IPR-SRAM/QDRII
• Description: IP CORE Renewal Of IP-SRAM/QDRII
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SRAM/QDRII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: HardCopy II, Stratix
• Features: Automatic Concatenation Of Consecutive Reads And Writes, Easy-to-Use IP Toolbench Interface
• Core Architecture: FPGA
• Core Sub-architecture: HardCopy, Stratix
• Rohs Compliant: NA
• Function: QDRII SRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Parameters
Altera Corporation
November 2009
f
The testbench instantiates a QDRII SRAM model, a reference clock for the
PLL, and model for the system board memory trace delays.
Altera provides a Verilog HDL simulation model. The model is a
behavioral model to verify the design but does not simulate any delays.
Altera recommends that you replace the model with the specific model
from your memory vendor.
For more details on how to run the simulation script, refer to
the Example Design” on page
Constraints
IP Toolbench generates a constraints script,
add_constraints_for_<variation name>.tcl, which is a set of Quartus II
assignments that are required to successfully compile the example
design.
1
The constraints script implements the following types of assignments:
■
■
■
■
■
The parameters can only be set in IP Toolbench (refer to
Parameterize” on page
cqn, cq, and q capture pins placement
Capacitance loading
cq pin set to non-global signal
I/O type for all interface pins
Cut timing assignments for false timing paths
When the constraints script runs, it creates another script,
remove_constraints_for_<variation name>.tcl, which you can
use to remove the constraints from your design.
MegaCore Version 9.1
QDRII SRAM Controller MegaCore Function User Guide
2–5).
2–11.
Functional Description
“Step 1:
“Simulate
3–29