IPR-SRAM/QDRII Altera, IPR-SRAM/QDRII Datasheet - Page 52

• Manufacturer Part Number: IPR-SRAM/QDRII
• Description: IP CORE Renewal Of IP-SRAM/QDRII
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SRAM/QDRII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: HardCopy II, Stratix
• Features: Automatic Concatenation Of Consecutive Reads And Writes, Easy-to-Use IP Toolbench Interface
• Core Architecture: FPGA
• Core Sub-architecture: HardCopy, Stratix
• Rohs Compliant: NA
• Function: QDRII SRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Interfaces & Signals
Figure 3–17. Simultaneous Read & Write—Burst of Four (Narrow Mode)
3–20
QDRII SRAM Controller MegaCore Function User Guide
avl_wait_request_wr
avl_wait_request_rd
avl_data_read_valid
avl_data_wr[17:0]
avl_data_rd[17:0]
avl_adr_wr[19:0]
avl_adr_rd[19:0]
qdrii_a[19:0]
qdrii_d[17:0]
qdrii_q[17:0]
qdrii_wpsn
qdrii_rpsn
qdrii_cqn
avl_read
avl_write
qdrii_cq
qdrii_k
avl_clk
1000 1001
3000 3001 3002 3003
1112 1314 1516 1718
Burst of Two
For the burst of two, the protocol already allows simultaneous reads and
writes by asserting readn and writen and their respective addresses for
only half a clock cycle. No arbitration on the Avalon interface is required
and you can use the full bandwidth, without even losing any initial
cycles.
burst of two configuration.
1002
1718
Figure 3–18 on page 3–21
1003
MegaCore Version 9.1
3000 1000 3002 1002
11 12 13 14 15 16 17 18
shows concurrent reads and writes in a
01 02 03 04 05 06 07 08
18
08
Altera Corporation
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November 2009
0708