DS26514DK Maxim Integrated Products, DS26514DK Datasheet - Page 153

• Manufacturer Part Number: DS26514DK
• Description: Power Management Modules & Development Tools 4-Port T1-E1-J1 Tran Transceiver Demo Kit
• Manufacturer: Maxim Integrated Products

Specifications of DS26514DK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 0: Receive DS0 Channel Bits (B[1:8]). Receive channel data that has been selected by the Receive
Channel Monitor Select Register (RDS0SEL). B8 is the LSB of the DS0 channel (last bit to be received).
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Note: This register has an alternate definition for E1 mode. See E1RRTS7.
Bit 7: Receive FDL Bit 7 (RFDL7). MSB of the received FDL code.
Bit 6: Receive FDL Bit 6 (RFDL6).
Bit 5: Receive FDL Bit 5 (RFDL5).
Bit 4: Receive FDL Bit 4 (RFDL4).
Bit 3: Receive FDL Bit 3 (RFDL3).
Bit 2: Receive FDL Bit 2 (RFDL2).
Bit 1: Receive FDL Bit 1 (RFDL1).
Bit 0: Receive FDL Bit 0 (RFDL0). LSB of the received FDL code.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Note: This register has an alternate definition for T1 mode. See T1RFDL. All bits in this register are real-time (not latched).
Bits 7 to 3: CRC-4 Sync Counter Bits (CSC[5:2] and CSC0). The CRC-4 sync counter increments each time the
8ms CRC-4 multiframe search times out. The counter is cleared when the framer has successfully obtained
synchronization at the CRC-4 level. The counter can also be cleared by disabling the CRC-4 mode (RCR1.3 = 0).
This counter is useful for determining the amount of time the framer has been searching for synchronization at the
CRC-4 level. ITU-T G.706 suggests that if synchronization at the CRC-4 level cannot be obtained within 400 ms,
then the search should be abandoned and proper action taken. The CRC-4 sync counter will saturate (not rollover).
CSC0 is the LSB of the 6–bit counter. (Note: CSC1 is omitted to allow resolution to > 400ms using 5 bits.)
Bit 2: CRC-4 MF Sync Active (CRC4SA). Set while the synchronizer is searching for the CRC-4 MF alignment
word.
Bit 1: CAS MF Sync Active (CASSA). Set while the synchronizer is searching for the CAS MF alignment word.
Bit 0: FAS Sync Active (FASSA). Set while the synchronizer is searching for alignment at the FAS level.
Rev: 101608
RFDL7
CSC5
B1
7
0
7
0
7
0
RDS0M
Receive DS0 Monitor Register
060h + (200h x (n - 1)) : where n = 1 to 4
T1RFDL (T1 Mode)
Receive FDL Register
062h + (200h x (n - 1)) : where n = 1 to 4
E1RRTS7 (E1 Mode)
Receive Real-Time Status Register 7
062h + (200h x (n - 1)) : where n = 1 to 4
RFDL6
CSC4
B2
6
0
6
0
6
0
RFDL5
CSC3
B3
5
0
5
0
5
0
RFDL4
CSC2
B4
4
0
4
0
4
0
RFDL3
CSC0
B5
3
0
3
0
3
0
DS26514 4-Port T1/E1/J1 Transceiver
CRC4SA
RFDL2
B6
2
0
2
0
2
0
CASSA
RFDL1
B7
1
0
1
0
1
0
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FASSA
RFDL0
B8
0
0
0
0
0
0