DS26514DK Maxim Integrated Products, DS26514DK Datasheet - Page 92

• Manufacturer Part Number: DS26514DK
• Description: Power Management Modules & Development Tools 4-Port T1-E1-J1 Tran Transceiver Demo Kit
• Manufacturer: Maxim Integrated Products

Specifications of DS26514DK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The device couples to the receive E1 or T1 twisted pair (or coaxial cable in 75Ω E1 applications) via a 1:1 or 2:1
transformer. See
Receive sensitivity is configurable by setting the appropriate RSMS[1:0] bits (LRCR).
The DS26514 uses a digital clock recovery system. The resultant E1, T1 or J1 clock derived from MCLK is
multiplied by 16 via an internal PLL and fed to the clock recovery system. The clock recovery system uses the
clock from the PLL circuit to form a 16 times oversampler, which is used to recover the clock and data. This
oversampling technique offers outstanding performance to meet jitter tolerance specifications shown in
Figure
Normally, the clock that is output at the RCLKn pin is the recovered clock from the E1 AMI/HDB3 or T1 AMI/B8ZS
waveform presented at the RTIPn and RRINGn inputs. If the jitter attenuator (LTRCR) is placed in the receive path
(as is the case in most applications), the jitter attenuator restores the RCLKn to an approximate 50% duty cycle. If
the jitter attenuator is either placed in the transmit path or is disabled, the RCLKn output can exhibit slightly shorter
high cycles of the clock. This is due to the highly over-sampled digital clock recovery circuitry. See
more details. When no signal is present at RTIPn and RRINGn, a receive carrier loss (RCL) condition will occur
and the RCLKn will be derived from the MCLKT1 or MCLKE1 source (depending on the configuration).
9.12.3.2
The DS26514 will report the signal strength at RTIPn and RRINGn in approximately 2.5dB increments via RSL[3:0]
located in the LIU Receive Signal Level Register (LRSL). This feature is helpful when trouble shooting line
performance problems.
9.12.3.3
The DS26514 can receive a 2.048MHz square-wave synchronization clock as specified in Section 10 of ITU-T
G.703. To use this mode, set the receive G.703 clock bit (RG703) found in the LIU Receive Control Register
(LRCR.7).
9.12.3.4
The receive equalizer is equipped with a monitor mode function that is used to overcome the signal attenuation
caused by the resistive bridge used in monitoring applications. This function allows for a resistive gain of up to
32dB along with cable attenuation of 12dB to 30dB as shown in the LIU Receive Control Register (LRCR).
Rev: 101608
9-27.
Receive Level Indicator
Receive G.703 Section 10 Synchronization Signal
Receiver Monitor Mode
Table 9-41
RECEIVE LIU
R
T
for transformer details.
R
T
RRINGn
RTIPn
LRISMR.RIMPON
TFR
1:1
DS26514 4-Port T1/E1/J1 Transceiver
Rx LINE
Table 13-3
92 of 305
for