DS26514DK Maxim Integrated Products, DS26514DK Datasheet - Page 6

• Manufacturer Part Number: DS26514DK
• Description: Power Management Modules & Development Tools 4-Port T1-E1-J1 Tran Transceiver Demo Kit
• Manufacturer: Maxim Integrated Products

Specifications of DS26514DK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS26514 4-Port T1/E1/J1 Transceiver
Figure 11-16. T1 Transmit-Side TCHCLKn Gapped Mode During F-Bit ................................................................. 273
Figure 11-17. E1 Receive-Side Timing.................................................................................................................... 274
Figure 11-18. E1 Receive-Side Boundary Timing (Elastic Store Disabled) ............................................................ 274
Figure 11-19. E1 Receive-Side 1.544MHz Boundary Timing (Elastic Store Enabled)............................................ 275
Figure 11-20. E1 Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled)............................................ 275
Figure 11-21. E1 Receive-Side Interleave Bus Operation—BYTE Mode ............................................................... 276
Figure 11-22. E1 Receive-Side Interleave Bus Operation—FRAME Mode ............................................................ 277
Figure 11-23. E1 Receive-Side RCHCLKn Gapped Mode During Channel 1 ........................................................ 277
Figure 11-24. E1 Transmit-Side Timing................................................................................................................... 278
Figure 11-25. E1 Transmit-Side Boundary Timing (Elastic Store Disabled) ........................................................... 278
Figure 11-26. E1 Transmit-Side 1.544MHz Boundary Timing (Elastic Store Enabled)........................................... 279
Figure 11-27. E1 Transmit-Side 2.048MHz Boundary Timing (Elastic Store Enabled)........................................... 279
Figure 11-28. E1 Transmit-Side Interleave Bus Operation—BYTE Mode .............................................................. 280
Figure 11-29. E1 Transmit-Side Interleave Bus Operation—FRAME Mode ........................................................... 281
Figure 11-30. E1 G.802 Timing ............................................................................................................................... 282
Figure 11-31. E1 Transmit-Side TCHCLKn Gapped Mode During Channel 1 ........................................................ 282
Figure 13-1. SPI Interface Timing Diagram ............................................................................................................. 286
Figure 13-2. Intel Bus Read Timing (BTS = 0) ........................................................................................................ 288
Figure 13-3. Intel Bus Write Timing (BTS = 0)......................................................................................................... 288
Figure 13-4. Motorola Bus Read Timing (BTS = 1) ................................................................................................. 289
Figure 13-5 Motorola Bus Write Timing (BTS = 1) .................................................................................................. 289
Figure 13-6. Receive Framer Timing—Backplane (T1 Mode)................................................................................. 291
Figure 13-7. Receive-Side Timing—Elastic Store Enabled (T1 Mode) ................................................................... 292
Figure 13-8. Transmit Formatter Timing—Backplane ............................................................................................. 294
Figure 13-9. Transmit Formatter Timing—Elastic Store Enabled............................................................................ 295
Figure 13-10. BPCLK1 Timing................................................................................................................................. 295
Figure 13-11. JTAG Interface Timing Diagram........................................................................................................ 296
Figure 14-1. JTAG Functional Block Diagram ......................................................................................................... 297
Figure 14-2. TAP Controller State Diagram............................................................................................................. 300
Rev: 101608
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