DS26514DK Maxim Integrated Products, DS26514DK Datasheet - Page 25

• Manufacturer Part Number: DS26514DK
• Description: Power Management Modules & Development Tools 4-Port T1-E1-J1 Tran Transceiver Demo Kit
• Manufacturer: Maxim Integrated Products

Specifications of DS26514DK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AL/RSIGF/FLOS1
Rev: 101608
D[5]/SPI_SWAP
D[2]/SPI_SCLK
D[1]/SPI_MOSI
D[0]/SPI_MISO
SPI_SEL/
NAME
MCLK
WRB/
RDB/
RWB
INTB
CSB
DSB
BTS
D[4]
D[3]
M13
PIN
M9
M8
R8
P8
N8
R7
R9
C3
B7
T8
L9
T7
Input with
Stateable
pulldown/
Output,
internal
Output
Output
Output
Output
Output
Output
Ouput
TYPE
Input/
Input/
Input/
Input/
Input/
Input/
Input
Input
Input
Input
Input
Tri-
Data [5]/SPI Bit Order Swap
D[5]: Bit 5 of the 16-bit or 8-bit data bus used to input data during register writes
and data outputs during register reads. Not driven when CSB = 1.
SPI_SWAP: This signal is active when SPI_SEL = 1. The address and data bit
order is swapped when SPI_SWAP is high. The R/W and B bit positions are
never changed in the control word.
Data [4]. Bit 4 of the 8-bit data bus used to input data during register writes and
data outputs during register reads. Not driven when CSB = 1.
Data [3]. Bit 3 of the 8-bit data bus used to input data during register writes and
data outputs during register reads. Not driven when CSB = 1.
Data [2]/SPI Serial Interface Clock
D[2]: Bit 2 of the 8-bit data bus used to input data during register writes and data
outputs during register reads. Not driven when CSB = 1.
SPI_SCLK: SPI Serial Clock Input when SPI_SEL = 1.
Data [1]/SPI Serial Interface Data Master Out-Slave In
D[1]: Bit 1 of the 8-bit data bus used to input data during register writes, and data
outputs during register reads. Not driven when CSB = 1.
SPI_MOSI: SPI Serial Data Input (Master Out-Slave In) when SPI_SEL = 1.
Data [0]/SPI Serial Interface Data Master In-Slave Out
D[0]: Bit 0 of the 8-bit data bus used to input data during register writes and data
outputs during register reads. Not driven when CSB = 1.
SPI_MISO: SPI Serial Data Output (Master In-Slave Out) when SPI_SEL = 1.
Chip-Select Bar. This active-low signal is used to qualify register read/write
accesses. The RDB/DSB and WRB signals are qualified with CSB.
Read Bar/Data-Strobe Bar. This active-low signal along with CSB qualifies read
access to one of the DS26514 registers. The DS26514 drives the data bus with
the contents of the addressed register while RDB and CSB are low.
Write Bar/Read-Write Bar. This active-low signal along with CSB qualifies write
access to one of the DS26514 registers. Data at D[7:0] is written into the
addressed register at the rising edge of WRB while CSB is low.
Interrupt Bar. This active-low output is asserted when an unmasked interrupt
event is detected. INTB will be deasserted (and tri-stated) when all interrupts
have been acknowledged and serviced. Extensive mask bits are provided at the
global level, framer, LIU, and BERT level.
SPI Serial Bus Mode Select/Analog Loss/Receive Signaling Freeze/Framer
LOS
SPI_SEL: 0 = Parallel Bus Mode, 1 = SPI Serial Bus Mode
AL/RSIGF/FLOS1: Analog LOS reflects the loss of signal detected by the LIU
front-end; framer LOS is LOS detection by the corresponding framer. The same
pins can reflect receive-signaling freeze indications. This selection can be made
by settings in Global Transceiver Control Register (GTCR1). AL/RSIGF/FLOS1
are available by setting the GTCR1.528MD bit to 1.
Bus Type Select. Set high to select Motorola bus timing, low to select Intel bus
timing. This pin controls the function of the RDB/DSB and WRB pins. Note: If SPI
mode is selected by the SPI_SEL pin, this pin must be tied low.
Master Clock. This is an independent free-running clock whose input can be a
multiple of 2.048MHz ±50ppm or 1.544MHz ±50ppm. The clock selection is
available by bits MPS0 and MPS1 and FREQSEL. Multiple of 2.048MHz can be
internally adapted to 1.544MHz. Multiple of 1.544MHz can be adapted to
2.048MHz. Note that TCLKn must be 2.048MHz for E1 and 1.544MHz for T1/J1
operation. See
0 = LSB is transmitted and received first.
1 = MSB is transmitted and received first.
SYSTEM INTERFACE
Table
10-15.
FUNCTION
DS26514 4-Port T1/E1/J1 Transceiver
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