AD9739BBCRL Analog Devices Inc, AD9739BBCRL Datasheet
AD9739BBCRL
Specifications of AD9739BBCRL
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AD9739BBCRL Summary of contents
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FEATURES Dynamic performance DOCSIS 3.0 performance 8 QAM carriers @ 400 MHz IF: −71 dBc 16 QAM carriers @ 400 MHz IF: −68 dBc 32 QAM carriers @ 400 MHz IF: −65 dBc 72 QAM carriers @ 600 MHz IF: ...
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AD9739 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 DC Specifications ......................................................................... 3 Digital Specifications ................................................................... 4 AC Specifications ...
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SPECIFICATIONS DC SPECIFICATIONS VDDA = VDD33 = 3.3 V, VDDC = VDD = 1 Table 1. Parameter RESOLUTION ACCURACY Integral Nonlinearity (INL) Differential Nonlinearity (DNL) ANALOG OUTPUTS Gain Error (with Internal Reference) Full-Scale Output Current Output Compliance Range ...
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AD9739 DIGITAL SPECIFICATIONS VDDA = VDD33 = 3.3 V, VDDC = VDD = 1 link, unless otherwise noted. Table 2. Parameter LVDS DATA INPUTS (DB0[13:0]P, DB0[13:0]N, DB1[13:0]P, DB1[13:0]N) DB Input Voltage Range ...
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Parameter INPUTS (SDI, SDIO, SCLK, CS) Voltage in High Voltage in Low Current in High Current in Low SDIO Output Voltage Out High Voltage Out Low Current Out ...
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AD9739 Parameter NOISE SPECTRAL DENSITY (NSD) Single Tone 2400 MSPS DAC f = 100 MHz OUT f = 350MHz OUT f = 550 MHz OUT f = 850 MHz OUT Eight-Tone 2400 MSPS, 500 kHz Tone ...
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ABSOLUTE MAXIMUM RATINGS Table 4. With Parameter Respect To Rating VDDA VSSA −0 +3.6 V VDD33 VSS −0 +3.6 V VDD VSS −0 +1.98 V VDDC VSSC −0 +1.98 V VSSA VSS ...
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AD9739 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VDDA, 3.3V, ANALOG SUPPLY VSSA, ANALOG SUPPLY GROUND VSSA SHIELD, ...
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Table 6. AD9739 Pin Function Descriptions Pin No. C1, C2, D1, D2, E1, E2, E3, E4 A1, A2, A3, A4, A5, B1, B2, B3, B4, B5, ...
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AD9739 Pin No. L1, M1 L2, M2 L3, M3 L4, M4 L5, M5 L6, M6 L7, M7 L8, M8 L9, M9 L10, M10 L11, M11 L12, M12 L13, M13 L14, M14 N1, P1 N2, P2 N3, P3 N4, P4 N5, ...
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TYPICAL PERFORMANCE CHARACTERISTICS STATIC LINEARITY 3.0 2.5 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 –2.5 –3.0 0 2048 4096 6144 8192 10,240 12,288 14,336 16,384 CODE Figure 7. Typical INL 25°C 1.0 0.5 0 –0.5 ...
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AD9739 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 –2.5 –3.0 0 2048 4096 6144 8192 10,240 12,288 14,336 16,384 CODE Figure 13. Typical INL 25°C 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 –2.5 –3.0 0 ...
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DYNAMIC PERFORMANCE NORMAL MODE FULL SCALE (UNLESS OTHERWISE NOTED) START 20MHz VBW 10kHz Figure 18. Single Tone Spectrum @ MHz, f OUT START 20MHz VBW 10kHz Figure 19. Single Tone Spectrum @ f = 1091 ...
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AD9739 90 80 10mA 20mA 100 200 300 400 500 600 f (MHz) OUT Figure 24. SFDR vs. f over ANAFS @ 2.0 GSPS OUT –40°C 60 +25°C 50 ...
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OUT Figure 30. Single-Tone NSD vs. f over f OUT –160 –161 ...
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AD9739 CENTER 350.27MHz #RES BW 30kHz SWEEP 174.6ms (601pts) VBW 300kHz FREQ REF RMS RESULTS OFFSET BW LOWER (MHz) (MHz) (dBc) (dBm) CARRIER POWER 5 3.84 –79.90 –94.44 –14.54dBm/ 10 3.84 –80.60 –95.14 3.84MHz 15 3.84 –80.90 –95.45 20 3.84 ...
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DYNAMIC PERFORMANCE MIX MODE FULL SCALE START 20MHz #RES BW 10kHz VBW 10kHz Figure 37. Single-Tone Spectrum in Mix Mode @ 2.4 GSPS DAC START 20MHz START 20MHz #RES BW 10kHz VBW 10kHz Figure 38. ...
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AD9739 CENTER 2.807GHz #RES BW 30kHz SWEEP 174.6ms (601pts) VBW 300kHz FREQ REF RMS RESULTS OFFSET BW LOWER (MHz) (MHz) (dBc) (dBm) CARRIER POWER 5 3.84 –64.90 –89.30 –24.4dBm/ 10 3.84 –66.27 –90.67 3.84MHz 15 3.84 –68.44 –92.84 20 3.84 ...
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DOCSIS PERFORMANCE 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 0 100 200 300 400 500 600 f (MHz) OUT Figure 46. Single-Carrier DOCSIS ACLR Spectral Plot @ 91 MHz (DOCSIS SPEC (Red Line dBc ; ...
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AD9739 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 0 100 200 300 400 500 600 f (MHz) OUT Figure 52. Single-Carrier DOCSIS ACLR Spectral Plot @ 825 MHz (DOCSIS SPEC (Red Line dBc ; Harmonic ...
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OUT Figure 58. Four-Carrier DOCSIS ACLR Spectral Plot @ 325 MHz (DOCSIS SPEC (Red Line dBc ; Harmonic Exception Is ...
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AD9739 0 –10 –20 –30 –40 –50 –60 –70 –80 0 100 200 300 400 500 600 F (MHz) OUT Figure 64. Eight-Carrier DOCSIS ACLR Spectral Plot @ 100 MHz (DOCSIS SPEC (Red Line dBc; Harmonic Exception Is ...
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OUT Figure 70. 32-Carrier DOCSIS ACLR Spectral Plot @ 900 MHz (DOCSIS SPEC (Red Line dBc; Harmonic Exception Is 42 ...
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AD9739 TERMINOLOGY Linearity Error (Integral Nonlinearity or INL) The maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale. Differential Nonlinearity (DNL) The measure of the variation in ...
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THEORY OF OPERATION The AD9739 is a 14-bit DAC that operates at an update rate 2.5 GSPS. Due to internal timing requirements, the minimum allowable sample rate is 800 MSPS. Input data is sampled through two 14-bit ...
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AD9739 MSB/LSB TRANSFERS The AD9739 serial port can support both MSB-first and LSB- first data formats. This functionality is controlled by LSB/MSB at Register 0x00, Bit 6. The default is MSB first (LSB/MSB = 0). When LSB/MSB = 0 (MSB ...
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SPI REGISTER MAP Table 7. Name Address Bit 7 Bit 6 Mode 0x00 SDIO_DIR LSB/MSB Power- 0x01 N/A N/A Down CNT_CLK_ 0x02 N/A N/A Dis IRQ_En 0x03 N/A N/A IRQ_Req 0x04 N/A N/A RSVD 0x05 N/A N/A FSC_1 0x06 FSC[7] ...
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AD9739 Name Address Bit 7 Bit 6 LVDS_ 0x1F SYNCSH_ N/A DEL[0] REC_STAT7 LVDS_ 0x20 SYNCSH_ SYNCSH_ DEL[8] DEL[7] REC_STAT8 LVDS_ 0x21 SYNC_TRK SYNC_INIT _ON _ON REC_STAT9 CROSS_ 0x22 N/A N/A CNT1 CROSS_ 0x23 N/A N/A CNT2 PHS_DET 0x24 N/A ...
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Table 11. Power-Down Register Bit Descriptions Bit Name Read/Write LVDS_DCO_PD Read/write LVDS_RCVR_PD Read/write CLK_REC_PD Read/write DAC_BIAS_PD Read/write Table 12. Controller Clock Disable Register (Register 0x02) Register 1 Name Address Bit 7 CNT_CLK_Dis 0x02 02 N/A 1 The two-digit number is ...
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AD9739 Bit Name Read/Write Description MULCK_IRQ Read 0: the mu controller is unlocked. 1: the mu controller has achieved lock and an interrupt has occurred. RCVLST_IRQ Read 0: the RCV controller has not lost lock. 1: the RCV controller has ...
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Table 21. LVDS Control/Status Register Bit Descriptions Bit Name Read/Write Description Read/write HNDOFF_CHK_RST 0: default. Bit is in the inactive state. 1: resets the handoff errors in Register 0x0B. LVDS_Bias[1:0] Read/write 0x0: 360 μA bias current. 0x1: 460 μA bias ...
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AD9739 Table 22. LVDS Receiver Control Registers (Register 0x10, Register 0x11, Register 0x12, Register 0x13, Register 0x14, Register 0x15, Register 0x16, Register 0x17, Register 0x18) Register 1 Name Address Bit 7 LVDS_ 0x10 16 SYNC_ FLG_RST REC_CNT1 LVDS_ 0x11 17 ...
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Table 24. LVDS Receiver Status Registers (Register 0x19, Register 0x1A, Register 0x1B, Register 0x1C, Register 0x1D, Register 0x1E, Register 0x1F, Register 0x20, Register 0x21) Register 1 Name Address Bit 7 LVDS_ 0x19 25 SMP_DEL[1] REC_STAT1 LVDS_ 0x1A 26 SMP_DEL[9] REC_STAT2 ...
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AD9739 Bit Name Read/Write Description RCVR_FE_ON Read 0: indicates that the FINDEDGE state machine is not active. 1: indicates that the FINDEDGE state machine is active. RCVR_LST_LCK Read 0: lock has not been lost. 1: lock has been lost at ...
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Table 29. MU Controller Register Bit Descriptions Bit Name Read/Write Description PHS_DET Read/write 0: no action. AUTO_EN 1: enables phase detector correction (recommended to always enable). CMP_BST Read/write 0: no action. 1: enables the phase detector comparator boost (only valid ...
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AD9739 Bit Name Read/Write Description Retry Read/write 0x0: if the correct value is not found, the search stops. 0x1: if the correct value is not found, the search begins again. Search_Tol Read/write 0x0: not exact (can find a phase within ...
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APPLICATIONS INFORMATION ANALOG MODES OF OPERATION The AD9739 uses the quad-switch architecture shown in Figure 80, which can be configured to operate in one of the following three modes via the serial peripheral interface: normal mode, RZ mode, and analog ...
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AD9739 The SYNC_IN_x and SYNC_OUT_x signals are used to synchronize multiple parts (see the Synchronization Controller section for more information). Each data port runs internally at half the speed of the DACCLK_x, and the two ports are subse- quently multiplexed ...
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CLOCKING THE AD9739 To provide the required signal swing for the internal clock receiver of the AD9739 necessary to use an external clock buffer chip to drive the DACCLK_P and DACCLK_N inputs. The recommended clock buffer for this ...
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AD9739 Clock Phase Noise Affects on AC Performance The quality of the clock source driving the determines the achievable ACLR performance for the AD9739. Table 32 summarizes the close-in ACLR for an eight-carrier DOCSIS signal at 920 MHz with respect ...
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MU DELAY CONTROLLER The mu delay controller adjusts timing between the digital and analog blocks. The mu delay controller maintains phase relational information between the digital and analog clock domains. The control system continuously adjusts the mu delay to maintain ...
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AD9739 To determine the correct slope, the controller measures the slope by first incrementing and then decrementing the mu delay value until any of the following happens: • The phase changes by 2. • The phase is equal to 16 ...
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SYNCHRONIZATION CONTROLLER A top level diagram of the synchronization circuitry and controller is shown in Figure 92. The synchronization circuitry requires a sync signal into the DAC (SYNC_IN_x) to set the clock divider. The frequency of the SYNC_IN_x signal must ...
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AD9739 Operation in Master Mode Setting Register 0x10, Bit 5 high sets the controller to master mode. This enables the sync logic to enter an initialization phase that adjusts the SYNC_OUT_x delay. By moving the SYNC_OUT_x delay, the SYNC_IN_x sampling ...
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SYNC_IN_x Status bits are available in the SPI to verify that the synchron- ization controller has found lock (Register 0x21, Bit 4), that the synchronization controller has entered tracking mode (Register 0x21, Bit 7), and whether the controller has lost ...
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AD9739 by the DCI transition detection, and then back into track mode. Status bits are available in the SPI to verify that the receiver controller has found lock (Register 0x21, Bit 0), that the receiver controller has entered tracking mode ...
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MaxSkew + Jitter = 800 ps – 344 ps – 100 ps MaxSkew + Jitter = 456 ps OPTIMIZING THE CLOCK COMMON-MODE VOLTAGE To optimize the interface and handoff timing, there is an additional system that sets the common-mode voltage ...
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AD9739 200 400 600 DAC GAIN CODE Figure 103. IFS vs. DAC Gain Code Always connect a 10 kΩ resistor from the I120 pin to ground and use the digital controls ...
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The differential voltage existing between IOUTP and IOUTN can also be converted to a single-ended voltage via a transformer or differential amplifier configuration. Internal to the AD9739 is a differential resistance between IOUTP and IOUTN that must be factored into ...
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AD9739 RECOMMENDED START-UP SEQUENCE The steps necessary to optimize the performance of the part and generate an output waveform are as follows: 1. Enable clocks to the controller and set the full-scale current. The registers and bits used in this ...
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Table 40. 1 Register Address Bit 7 Bit 6 PHS_DET 0x24 36 N/A N/A MU_DUTY 0x25 37 MU_DUTY POS/NEG (0) AUTO_EN (1) MU_CNT1 0x26 38 N/A Slope (0) MU_CNT2 0x27 39 MUDEL[0] SrchMode[1] (0) (1) MU_CNT3 0x28 40 MUDEL[8] MUDEL[7] ...
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AD9739 To verify that the sync controller is locked and tracking, the following bits must be read back: • Register 0x21, Bit 4 (SYNC_LCK)—If the controller is locked, this bit reads back a value of 1. This is a value ...
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... OUTLINE DIMENSIONS 1.40 MAX ORDERING GUIDE Model Temperature Range 1 AD9739BBCZ −40°C to +85°C 1 AD9739BBCZRL −40°C to +85°C AD9739BBC −40°C to +85°C AD9739BBCRL −40°C to +85°C 1 AD9739-EBZ 1 AD9739-MIX-EBZ 1 AD9739-CMTS-EBZ RoHs Compliant Part. 12.10 12. 11. BALL A1 INDICATOR 10.40 TOP VIEW BSC SQ 0 ...
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AD9739 NOTES Rev Page ...
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NOTES Rev Page AD9739 ...
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AD9739 NOTES ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07851-0-1/09(0) Rev Page ...