AD9739BBCRL Analog Devices Inc, AD9739BBCRL Datasheet - Page 34
AD9739BBCRL
Manufacturer Part Number
AD9739BBCRL
Description
14 Bit 2.5 GSPS DAC
Manufacturer
Analog Devices Inc
Datasheet
1.AD9739BBCZ.pdf
(56 pages)
Specifications of AD9739BBCRL
Number Of Bits
14
Data Interface
Serial
Number Of Converters
1
Voltage Supply Source
Analog and Digital
Power Dissipation (max)
980mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
160-CSPBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Settling Time
-
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
AD9739
Bit Name
RCVR_FE_ON
RCVR_LST_LCK
RCVR_LCK
Table 26. Cross Controller Registers (Register 0x22, Register 0x23)
Register
Name
CROSS_
CNT1
CROSS_
CNT2
1
Table 27. Cross Controller Register Bit Descriptions
Bit Name
CLKP_OFFSET[3:0]
DIR_P
CLKN_OFFSET[3:0]
DIR_N
Table 28. MU Controller Registers (Register 0x24, Register 0x25, Register 0x26, Register 0x27, Register 0x28, Register 0x29,
Register 0x2A)
Register
Name
PHS_DET
MU_DUTY
MU_CNT1
MU_CNT2
MU_CNT3
MU_CNT4
MU_STAT1
1
The two-digit number is the decimal representation of the address.
The two-digit number is the decimal representation of the address.
Address
0x22
0x23
Address
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
34
35
36
37
38
39
40
41
42
1
1
Read/Write
Read/write
Read/Write
Read/write
Read/Write
Read/Write
Read
Read
Read
Bit 7
N/A
N/A
Bit 7
N/A
MU_DUTYAUTO_EN
N/A
MUDEL[0]
MUDEL[8]
Search_Tol
N/A
Description
0x0: programmable to vary the common-mode voltage for DACCLKP (for best ac
performance, the optimal setting is 15).
O: common-mode voltage on DACCLK_P decreases with the programmed value of
CLKP_OFFSET[3:0].
1: common-mode voltage on DACCLK_P increases with the programmed value of
CLKP_OFFSET[3:0] (for the best ac, the optimal setting is 0).
0x0: programmable to vary the common-mode voltage for DACCLKN (for best ac
performance, the optimal setting is 15).
O: common-mode voltage on DACCLK_N decreases with the programmed value
of CLKN_OFFSET[3:0].
1: common-mode voltage on DACCLK_N increases with the programmed value of
CLKN_OFFSET[3:0] (for the best ac, the optimal setting is 0).
Description
0: indicates that the FINDEDGE state machine is not active.
1: indicates that the FINDEDGE state machine is active.
0: lock has not been lost.
1: lock has been lost at some point.
0: the receiver controller is not locked.
1: the receiver controller is locked.
Bit 6
N/A
N/A
MUDEL[7]
Retry
N/A
Bit 6
N/A
POS/NEG
Slope
SrchMode[1]
Bit 5
N/A
N/A
Bit 5
PHS_DETAUTO_EN
ADJ[5]
Mode[1]
SrchMode[0]
MUDEL[6]
ContRst
N/A
Rev. 0 | Page 34 of 56
Bit 4
DIR_P
DIR_N
Bit 4
CMP_BST
ADJ[4]
Mode[0]
SetPhs[4]
MUDEL[5]
Guard[4]
N/A
Bit 3
CLKP_
OFFSET[3]
CLKN_
OFFSET[3]
Bit 3
Bias[3]
ADJ[3]
Read
SetPhs[3]
MUDEL[4]
Guard[3]
N/A
Bit 2
CLKP_
OFFSET[2]
CLKN_
OFFSET[2]
Bit 2
Bias[2]
ADJ[2]
Gain[1]
SetPhs[2]
MUDEL[3]
Guard[2]
N/A
Bit 1
CLKP_
OFFSET[1]
CLKN_
OFFSET[1]
Bias[1]
ADJ[1]
Gain[0]
SetPhs[1]
MUDEL[2]
Guard[1]
MU_LOST
Bit 1
Reset Value for
Write Register
0
0
0
Reset Value for
Write Register
0x0
0
0x0
0
Bit 0
CLKP_
OFFSET[0]
CLKN_
OFFSET[0]
Bit 0
Bias[0]
ADJ[0]
Enable
SetPhs[0]
MUDEL[1]
Guard[0]
MU_LKD